Junho Moon

Design of a 1.8 V 6-bit Folding Interpolation CMOS A/D Converter with a 0.93 [pJ/convstep] Figure-of-Merit

In this paper, a CMOS analog-to-digital converter (ADC) with a 6-bit 100MSPS at 1.8V is described. The architecture of the proposed ADC is based on a folding type with a resistive interpolation technique for low power consumption. To reduce the power consumption, a folder reduction technique to decrease the number of folding blocks (NFB) by half of the conventional ones, an averaging folder technique, and a compensated resistive interpolation technique are proposed. Further, an autoswitching encoder for efficient digital processing is also presented. With the clock speed of 100MSPS, the ADC achieves an effective resolution bandwidth (ERBW) of 50MHz, while consuming only 4.5mW of power. The measured result of figure-of-merit (FoM) is 0.93 [pJ/convstep]. The active chip occupies an area of 0.28mm2 in 0.18μm CMOS technology.

Design of a 6-bit 1GSPS fully folded CMOS A/D converter for Ultra Wide Band (UWB) applications

In this paper, a CMOS analog-to-digital converter (ADC) for Ultra Wide Band (UWB) applications with a 6-bit 1GSPS at 1.8 V is described. The architecture of the proposed ADC is based on a fully folded ADC using resistive interpolation technique for low power consumption. To reduce the power consumption, a folder reduction technique to decrease the number of folding blocks (NFB) is proposed. Further, a novel layout technique is introduced for compact area. With the clock speed of 1 GHz, the ADC achieves an effective resolution bandwidth (ERBW) of 200 MHz, while consuming only 60 mW of power. The measured INL and DNL are within plusmn0.7LSB, plusmn0.5LSB, respectively. The measured SNDR is 33.64 dB, when Fin=100 MHz at Fs=1 GHz. The active chip occupies an area of 0.27 mm2 in 0.18 mum CMOS technology.

12-bit 80MSPS double folding/interpolation A/D converter

In this paper, a CMOS analog-to-digital converter (ADC) with a 12-bit 80 MSPS at 1.8 V is designed. The architecture of the proposed ADC is based on a folding ADC with a double folding and interpolating structure. An even folding circuit technique for the high resolution and high speed ADC are introduced. Further, a novel auto-switching encoder is also proposed. The chip has been fabricated with 0.18 um 1-poly 6-metal CMOS technology. The active area is 1.6 mm2 and 195 mw at 1.8 V power supply. The DNL and INL are within plusmn4/plusmn4LSB, respectively. The measured result of SNDR is 46 dB, when Fin=1MHz at Fs=80 MHz.

Design of a 1.8V 6-bit 100MSPS 5mW CMOS A/D Converter with Low Power Folding-Interpolation Techniques

In this paper, CMOS analog-to-digital converter (ADC) with a 6-bit 100MSPS at 1.8V is described. The architecture of the proposed ADC is based on a folding type ADC using resistive interpolation technique for low power consumption. Further, the number of folding blocks (NFB) is decreased by half of them, compared to the conventional ones. With the clock speed of 100MSPS, the ADC achieves an effective resolution bandwidth (ERBW) of 50MHz, while consuming only 4.5mW of power. The measured result of figure-of-merit (FoM) is 0.93pJ/convstep. The active chip occupies an area of 0.28mm2 in 0.18mum CMOS technology

Design of a current steering CMOS D/A converter with an adaptive control switch and a novel layout technique

While the CMOS analog circuits can be designed with the minimum-gate-length of the fabrication process in the alpha-power law MOSFET model, the length of a MOSFET gate has been chosen to be a larger scale than the minimum-gate-length in the conventional Shockleypsilas square model. In this paper, we describe a 6-b 100 MSPS CMOS current steering digital-to-analog converter (DAC) with the alpha-power law model. In order to improve the matching characteristics of the DAC current cell, moreover, we introduce a new and unique adaptive-control-switch (ACS) and a common current cell layout technique using a tournament algorithm. The prototype circuit has been fabricated with a Samsung 1.8 V, 0.18 mum, 1-poly, 5-metal CMOS technology. It occupies 0.52 mm2 of silicon area with 15.8 mW power consumption. The fabricated chip area and the measured power dissipation are reduced by 30% and 25% over conventional ones, respectively.

A digitally self-calibrated low-noise 7-bit folding A/D converter

In this paper, a low noise 65nm 1.2V 7-bit 1GSPS A/D converter with a digitally self-calibrated technique is proposed. The A/D converter is based on a folding-interpolation structure whose folding rate is 2 and its interpolation rate is 8. A digitally self-calibrated technique with a feedback loop and a recursive digital code inspection is described. The circuit reduces the variation of the offset voltage, due to process mismatches, parasitic resistors, and parasitic capacitances. The chip has been fabricated with a 65nm 1-poly 6-metal CMOS technology. The effective chip area is 0.87mm2 and the power consumption is about 110mW with a 1.2V power supply. The measured SNDR is drastically improved in comparison with the same ADC without any calibration.

Design of a 1.8V 8-bit 1GSPS cascaded-folding CMOS A/D converter based on a folder averaging technique

In this paper, a CMOS analog-to-digital converter (ADC) with an 8-bit 1GSPS at 1.8V is designed. The architecture of the proposed ADC is based on a folding ADC with a cascaded-folding and an interpolation structure. A self-linearized preamplifier with source degeneration technique and a folder averaging technique for the high-performance are introduced. Further, a novel auto-switching encoder is also proposed. The chip has been fabricated with 0.18μm 1-poly 5-metal CMOS technology. The active chip area is 0.72mm2 and it consumes about 200mW at 1.8V power supply.

Design of a low power 10-bit cyclic D/A converter with a Johnson counter and a capacitor swapping technique

A cyclic 10-bit D/A converter based on a Johnson counter and a capacitor swapping technique is described. To reduce capacitor mismatching errors, two capacitors are alternately swapped according to input data. Further, a half differential architecture to reduce offset errors and a Johnson counter to improve the digital logic performance are proposed. With a 0.35μm Samsung CMOS technology, the measured SFDR is about 65dB, when the input frequency is 1MHz at a clock frequency of 2MHz. The power consumption is only 310μW at 3.3V power supply. The measured INL and DNL are within ±0.7LSB and ±0.75LSB, respectively.

A 1.8V 6-bit 1GS/s 60mW CMOS folding/interpolation ADC using folder reduction circuit and auto switching encoder

In this paper, CMOS analog-to-digital converter (ADC) with a 6-bit 1 GS/s at 1.8 V is described. The architecture of the proposed ADC is based on a folding type ADC using resistive interpolation technique for low power consumption. To reduce the power consumption, a folder reduction technique to decrease the number of folding blocks (NFB) by half of the conventional ones is proposed. Further, a novel layout technique is introduced for compact area. With the clock speed of 1 GS/s, the ADC achieves an effective resolution bandwidth (ERBW) of 200 MHz, while consuming only 60 mW, of power. The measured INL and DNL were within plusmn0.5 LSB, plusmn 0.7 LSB, respectively. The measured SNDR, was 33.82 dB, when the fin=100 MHz at Fs=500 MHz. The active chip occupies an area of 0.27 mm2 in 0.18 mum CMOS technology.

A 6b 100MS/s 0.28mm2 5mW 0.18um CMOS F/I ADC with a Novel Folder Reduction Technique

In this paper, CMOS analog-to-digital converter (ADC) with a 6-bit 100 MSPS at 1.8 V is described. The architecture of the proposed ADC is based on a folding type ADC using resistive interpolation technique for low power consumption. Further, the number of folding blocks (NFB) is decreased by half of them, compared to the conventional ones. With the clock speed of 100 MSPS, the ADC achieves an effective resolution bandwidth (ERBW) of 50 MHz, while consuming only 4.5 mW of power. The measured result of figure-of-merit (FoM) is 0.93 pJ/convstep. The active chip occupies an area of 0.28 mm2 in 0.18 mum CMOS technology.