Daihyun Lim

Extracting secret keys from integrated circuits

Modern cryptographic protocols are based on the premise that only authorized participants can obtain secret keys and access to information systems. However, various kinds of tampering methods have been devised to extract secret keys from conditional access systems such as smartcards and ATMs. Arbiter-based physical unclonable functions (PUFs) exploit the statistical delay variation of wires and transistors across integrated circuits (ICs) in manufacturing processes to build unclonable secret keys. We fabricated arbiter-based PUFs in custom silicon and investigated the identification capability, reliability, and security of this scheme. Experimental results and theoretical studies show that a sufficient amount of inter-chip variation exists to enable each IC to be identified securely and reliably over a practical range of environmental variations such as temperature and power supply voltage. We show that arbiter-based PUFs are realizable and well suited to build, for example, key-cards that need to be resistant to physical attacks.

A technique to build a secret key in integrated circuits for identification and authentication applications

This paper describes a technique that exploits the statistical delay variations of wires and transistors across ICs to build a secret key unique to each IC. To explore its feasibility, we fabricated a candidate circuit to generate a response based on its delay characteristics. We show that there exists enough delay variation across ICs implementing, the proposed circuit to identify individual ICs. Further. the circuit, functions reliably over a practical range of environmental variation such as temperature and voltage.

Identification and authentication of integrated circuits

This paper describes a technique to reliably and securely identify individual integrated circuits (ICs) based on the precise measurement of circuit delays and a simple challenge–response protocol. This technique could be used to produce key‐cards that are more difficult to clone than ones involving digital keys on the IC. We consider potential venues of attack against our system, and present candidate implementations. Experiments on Field Programmable Gate Arrays show that the technique is viable, but that our current implementations could require some strengthening before it can be considered as secure. Copyright

A 70GHz Manufacturable Complementary LC-VCO with 6.14GHz Tuning Range in 65nm SOI CMOS

A complementary LC-VCO is integrated in a 65nm SOI process and is statistically characterized on a 300mm wafer. Average center frequency is 67.9GHz and frequency tuning range is 6.14GHz or 9.05%. It achieves a phase noise of -106dBc/Hz at 10MHz offset and consumes 5.37mW from a 1.2V supply. The VCO yield is 94.7% for 70GHz operation.

Performance Variability of a 90GHz Static CML Frequency Divider in 65nm SOI CMOS

A static CML divide-by-2 frequency divider is integrated in 65nm SOI CMOS. The maximum operating frequency is 90GHz while dissipating 52.4mW. The self-oscillation frequency is 92GHz with 0.57pJ switching energy. Measurement of self-oscillation frequency at multiple bias conditions enables estimation of the variation in threshold voltage, capacitance, and resistance.

Performance and Yield Optimization of mm-Wave PLL Front-End in 65nm SOI CMOS

A combination of LC-VCO and 2:1 CML static frequency divider has been fabricated in 65 nm SOI CMOS technology and operates at 70 GHz. A cascoded buffer amplifier is used in VCO-to-divider connection to compensate for the power losses caused by interconnect parasitics, and inductive peaking is employed for bandwidth enhancement. The bias condition of the frequency divider has been tuned to find an optimal bias point in existence of VCO and frequency divider operating range variation. The inter-die variation of VCO and divider performance variations over a wafer and their correlation have been estimated.

A Data-Driven Statistical Approach to Analyzing Process Variation in 65nm SOI Technology

This paper presents a simple yet effective method to analyze process variations using statistics on manufacturing in-line data without assuming any explicit underlying model for process variations. Our method is based on a variant of principal component analysis and is able to reveal systematic variation patterns existing on a die-to-die and wafer-to-wafer level individually. The separation of die variation from wafer variation can enhance the understanding of a nature of the process uncertainty. Our case study based on the proposed decomposition method shows that the dominating die-to-die variation and wafer-to-wafer variation represent 31% and 25% of the total variance of a large set of in-line parameters in 65nm SOI CMOS technology

Early prediction of product performance and yield via technology benchmark

This paper presents a practical method to estimate IC product performance and parametric yield solely from a well-chosen set of existing electrical measurements intended for technology monitoring at an early stage of manufacturing. We demonstrate that the components of mmWave PLL and product-like logic performance in a 65 nm SOI CMOS technology are predicted within a 5% RMS error relative to mean.

An integrable low-cost hardware random number generator

A hardware random number generator is different from a pseudo-random number generator; a pseudo-random number generator approximates the assumed behavior of a real hardware random number generator. Simple pseudo random number generators suffices for most applications, however for demanding situations such as the generation of cryptographic keys, requires an efficient and a cost effective source of random numbers. Arbiter-based Physical Unclonable Functions (PUFs) proposed for physical authentication of ICs exploits statistical delay variation of wires and transistors across integrated circuits, as a result of process variations, to build a secret key unique to each IC. Experimental results and theoretical studies show that a sufficient amount of variation exits across IC’s. This variation enables each IC to be identified securely. It is possible to exploit the unreliability of these PUF responses to build a physical random number generator. There exists measurement noise, which comes from the instability of an arbiter when it is in a racing condition. There exist challenges whose responses are unpredictable. Without environmental variations, the responses of these challenges are random in repeated measurements. Compared to other physical random number generators, the PUF-based random number generators can be a compact and a low-power solution since the generator need only be turned on when required. A 64-stage PUF circuit costs less than 1000 gates and the circuit can be implemented using a standard IC manufacturing processes. In this paper we have presented a fast and an efficient random number generator, and analysed the quality of random numbers produced using an array of tests used by the National Institute of Standards and Technology to evaluate the randomness of random number generators designed for cryptographic applications.

Exploiting metastability and thermal noise to build a re-configurable hardware random number generator

While pseudo random number generators based on computational complexity are widely used for most of cryptographic applications and probabilistic simulations, the generation of true random numbers based on physical randomness is required to guarantee the advanced security of cryptographic systems. In this paper we present a method to exploit manufacturing variations, metastablity, and thermal noise in integrated circuits to generate random numbers. This metastability based physical random number generator provides a compact and low-power solution which can be fabricated using standard IC manufacturing processes. Test-chips were fabricated in TSMC 0.18um process and experimental results show that the generated random bits pass standard randomness tests successfully. The operation of the proposed scheme is robust against environmental changes since it can be re-calibrated to new environmental conditions such as temperature and power supply voltage.