Daisuke Ikebuchi

Ultra Fine-Grained Run-Time Power Gating of On-chip Routers for CMPs

This paper proposes an ultra fine-grained run-time power gating of on-chip router, in which power supply to each router component (e.g., VC queue, crossbar MUX, and output latch) can be individually controlled in response to the applied workload.As only the router components which are just transferring a packet are activated, the leakage power of the on-chip network can be reduced to the near-optimal level.However, a certain amount of wakeup latency is required to activate the sleeping components, and the application performance will be degraded.In this paper, we estimate the wakeup latency for each component based on circuit simulations using a 65nm process.Then we propose four early wakeup methods to overcome the wakeup latency.The proposed router with the early wakeup methods is evaluated in terms of the application performance, area, and leakage power.As a result, it reduces the leakage power by 78.9%, at the expense of the 4.3% area and 4.0% performance when we assume a 1GHz operation.

A fine-grain dynamic sleep control scheme in MIPS R3000

A fine-grain dynamic power gating is proposed for saving the leakage power in MIPS R3000 by sleep control and applied to a processor pipeline. An execution unit is divided into four small units: multiplier, divider, shifter and other (CLU). The power of each unit is cut off dynamically, based on the operation. We tape-outed the prototype chip Geyser-0, which provides an R3000 Core with the power reduction technique, 16 KB caches and translation lookaside buffer (TLB) using 90 nm CMOS technology. The evaluation results of four benchmark programs for embedded applications show that 47% of the leakage power is reduced on average with 41% area overhead.

Cool Mega-Arrays: Ultralow-Power Reconfigurable Accelerator Chips

Cool Mega-Array (CMA) is an energy-efficient reconfigurable accelerator for battery-driven mobile devices. It has a large processing-element array without memory elements for mapping an applications data-flow graph, a simple programmable microcontroller for data management, and data memory. Unlike coarse-grained dynamically reconfigurable processors, CMA reduces power consumption by switching hardware context and storing intermediate data in registers.

Geyser-1: a MIPS R3000 CPU core with fine-grained run-time power gating

Geyser-1 is a MIPS CPU which provides a fine-grained run-time power gating (PG) controlled by instructions. Unlike traditional PGs, it uses special standard cells in which the virtual ground (VGND) is separated from the real ground, and a certain number of the sleep transistors are inserted for quick power shut-down and wake-up. In Geyser-1, the fine-grained run-time PG is applied to computational modules in the execution stage. The power shut-down and wakeup are controlled with architectural and software level. This implementation is the first available CPU with this type of run-time PG technique. Geyser-1 has both time and spatial fine-grained PG and works well with a real chip.

Geyser-1: A MIPS R3000 CPU core with fine grain runtime power gating

Geyser-1, a prototype MIPS R3000 CPU with fine grain runtime PG for major computational components in the execution stage is available. Function units such as CLU, shifter, multiplier and divider are power-gated and controlled at runtime such that only the function unit to be used is powered-on to minimize the leakage power. The evaluation results on the real chip reveals that the fine grain runtime PG mechanism works without electric problems. It reduces the leakage power 7% at 25 °C and 24% at 80°C. The evaluation results using benchmark programs show that the power consumption can be reduced from 3% at 25 °C and 30% at 80°C.

Performance, Area, and Power Evaluations of Ultrafine-Grained Run-Time Power-Gating Routers for CMPs

This paper proposes the ultrafine-grained run-time power gating of on-chip routers, in which the power supply to each router component (e.g., virtual-channel buffer, virtual-channel multiplexer, and crossbar multiplexer and output latch) can be individually controlled based on the applied workload. Since only the router components that are transferring a packet are activated, the leakage power of the on-chip network can be reduced to a near-optimal level. However, such techniques inherently increase the communication latency and degrade the application performance, since a certain amount of wakeup latency is required to activate the sleeping components. To mitigate this wakeup latency, an early wakeup method that can preliminarily detect the next packet arrival and activate the corresponding components is essential. We designed and implemented an ultrafine-grained power-gating router using a commercial 65 nm process. We propose four early wakeup methods and combine them with the power-gating router. The proposed router with the early wakeup methods is evaluated in terms of its application performance, area overhead, and leakage power reduction taking into account the on/off energy overhead. The simulation results showed that it reduces the leakage power by 54.4-59.9% on average even when the application programs are fully running, at the expense of 4.6% of the area and 0.7-3.7% of the performance overheads when we assume a 1 GHz operation.

On-chip detection methodology for break-even time of power gated function units

In a fine-grain leakage saving technique to power gate function units, the efficiency is sensitive to overhead energy dissipating at turning on/off power switches. To get gain in energy savings, the powered-off period has to be longer than the minimum required time i.e. the break-even time (BET). While effectiveness of BET-aware power-gating control has been described in literatures, how to actually detect BET that fluctuates with the temperature and process variation has not been reported so far. This paper proposes an on-chip detection methodology for BET using pMOS/nMOS leakage monitors with MTCMOS circuit structure. We applied this methodology to the leakage monitors and a CPU including a power-gated multiplier implemented in 65nm CMOS technology. Results showed that our methodology detects BET at 5%–17% difference from that of the conventional simulation-based off-line technique.

Adaptive power gating for function units in a microprocessor

This paper describes adaptive fine-grain control to power gate function units based on temperature dependent break-even time (BET). An analytical model to express the temperature dependent BET is introduced and the accuracy of the model was examined. Results demonstrated that the model well represents the exponential decrease in BET with the temperature. Meanwhile, it was found that the accuracy gets worse at higher temperature and the cause is energy dissipation due to transient glitch at the wakeup. We propose four power-gating policies employing time-based or history-based approaches. Effectiveness in energy savings was evaluated using real design data of four function units in a microprocessor implemented in a 65nm technology. Results showed that introducing adaptive control to make use of temperature-dependent BET enhances energy savings by up to 21% in the time-based approach and by up to 18% in the history-based approach. The adaptive history-based policy with a limiter outperforms the adaptive time-based policy in energy savings and reduces the total energy of four function units to 11.8% at 100°C as compared to the non-power-gating case.

Cool Mega-Array: A highly energy efficient reconfigurable accelerator

A highly energy efficient reconfigurable accelerator called CMA (Cool Mega-Array) is proposed. It consists of a large Processing Element (PE) array without memory elements for maintain result of ALU and configuration data, a small simple programmable micro controller for data management, and the data memory. Unlike traditional coarse grained reconfigurable processors, the power consumption for hardware context switching, storing intermediate data in registers, and clock distribution for them are eliminated from PE array which occupies large area of a chip. Configuration registers are collected to small area of micro controller. The data flow graph mapped on the PE array is static during execution. Various application programs can be implemented by making the best use of flexible data management instructions with the micro controller. When the delay time in the PE array is longer than the data handling time with the micro controller, the supply voltage for the PE array is scaled to reduce the power consumption without degrading the performance. In the opposite case, wave pipelining is applied to enhance PE array performance. A prototype chip CMA-1 with 8 × 8 PE array with 24-bit data width was fabricated in 2.1 × 4.2mm2 65-nm CMOS technology, and achieves 2.4-GOPS/11.2-mW sustained performance. This energy efficiency is comparable to that of the most energy efficient accelerators that have been reported.

Geyser-2: the second prototype CPU with fine-grained run-time power gating

Geyser-2 is the second prototype MIPS CPU which provides a fine-grained run-time power gating (PG) controlled by instructions. Geyser-1[1], the first prototype only provides the fine-grained run-time PG core. Although it demonstrated the leakage power reduction on a real chip, the operational frequency is limited at 60MHz because of the limitation of the I/O speed. Geyser-2 with cache and TLB mechanism is implemented to show (1) run-time PG works at least with 200MHz which is commonly used clock for embedded systems, and (2) it is also efficient on the environment with real application programs with an operating system.