Masateru Koide

High-performance flip-chip BGA technology based on thin-core and coreless package substrate

A new organic build-up substrate packaging technology was developed in Fujitsu for high-end servers, where lower V-G impedance on substrate and thermal resistance are realized by applying metallic thermal injection materials. In the present paper, two important accomplishments in assembling process, eliminating voids with metallic thermal injection and controlling substrate flatness on mounting large LSIs, are investigated, and evaluated

Low warpage coreless substrate for large-size LSI packages

Due to inadequate rigidity, warpage of coreless substrates is generally large compared to other types of LSI package substrates. Therefore, the most important problem in the application of coreless substrates is warpage reduction during the reflow process. So far, there have been only a limited number of reports on coreless substrates for large-size LSI packages. Moreover, there have been very few examples that discussed substrate layer structure designs for warpage reduction and reliability improvement in the LSI assembly process. In the present study, we focus on developing coreless packages for large-size LSIs. To achieve our goal, we adopted the following development processes. First, we designed analytical models with different layer structures comprising two kinds of materials, and investigated the effect of layer structure on warpage reduction using warpage simulations. Next, we made four kinds of real coreless substrates with layer structures identical to the simulation models, and verified the actual thermal warpage behavior. Finally, we investigated the thermal stress reliabilities of these substrates after LSI mounting. From the results, we found that warpage reduction and reliability enhancement of coreless substrates were realized by arranging the high rigidity materials on the external layers of the substrates.

Precision improvement study of thermal warpage prediction technology for LSI packages

A finer interconnection pitch of LSI packages has enhanced the importance of precise prediction technology of temperature-dependent warpage. In our research, we prepared a model package with minute wiring and vias, and examined a method of improving the agreement accuracy between numerical analysis and measurement of temperature-dependent warpage. To improve the precision of warpage prediction technology, we paid attention to warpage measurement technology, especially the temperature distribution in a sample, in addition to improving the accuracy of the numerical analysis model and material properties. We succeeded in heating a substrate with a temperature difference of 20°C or 3°C between the top side and bottom side, by controlling the heating conditions. Furthermore, the numerical analysis with a fine wiring model was performed under conditions where the temperature varied in consideration of the thermal conductivity of the substrate. The material properties for the numerical analysis, such as Coefficient of Thermal Expansion and Relaxation Modulus were measured very carefully with original setups, because they are essential for improving the accuracy of our numerical analysis. As a result, we found that substrate warpage with an uneven temperature distribution is quite different from such warpage with uniform temperature. To predict the temperature-dependent warpage with a high accuracy, we found that the temperature distribution in a substrate should be considered in the numerical analysis, besides applying the precise model and material properties.

Development of second-level connection method for large-size CPU package

This paper reports on second-level interconnection development for a large-scale Ball Grid Array (BGA) package. Generally, control of warpage becomes a problem as BGA packages become larger. To solve this problem, the following two measures were executed. The first was adoption of a low-temperature solder, and the second was warpage control using a heat spreader as a fixture. We were able to decrease the reflow temperature to 200°C by applying the low-temperature solder, and the effect was a warp reduction of 200 μm. Moreover, the shape of the heat spreader was optimized through a thermal-stress simulation, obtaining a warp reduction of 100 μm. Verification with a test vehicle was executed, no short/opening was observed, and the results of a thermal cycle test and simulation confirmed there was no problem in reliability.

Development of CPU Package Embedded with Multilayer Thin Film Capacitor for Stabilization of Power Supply

This paper proposes a method of improving power delivery in a CPU package substrate with multilayer thin film capacitors (TFCs). Because TFC embedded technology can reduce the inductance of power delivery path, it can stabilize the power supply to the CPU. Higher permittivity, thinner layer thickness and wider conductor plane area results in larger capacitance. To further stabilize the power supply, we developed a package structure with an embedded double TFC layer that can double the capacitance. The double TFC embedded package was formed by laminating two TFCs to the top and bottom of the core layers in a build–up substrate. Through verification using test vehicles, it was confirmed that electrical performance was significantly improved with the double TFC. Also, it was demonstrated that the criteria of the capacitance and insulation resistance were satisfied in the product reliability tests.

Electrical characteristics of build-up substrates using new via structures

The electrical characteristics of the power supply path, which are influenced by the via structures in the build-up substrate were investigated. The build-up substrates are composed of core layers and build-up layers, connected by the plated through hole (PTH), and the build-up via (BU via), respectively. This paper investigates how the BU via structures affect the power supply path, and discusses the design constraints of the via structures in the build-up layers. Three design constraints were considered for the build-up substrate, which comprises six build-up layers laminated on both sides of the core layers. The first constraint limits the BU via stack number, the second is the propriety of the BU via stack on the PTH, and the last limits the number of BU vias connected on the PTH. By changing these design constraints, the power supply paths were designed and compared by simulation and measurement. As a result, the proposed via structure significantly reduced the resistance and inductance of the power supply path in the substrate, while yielding good connectivity and productivity.