Tomoyuki Akahoshi

Integrated 8×8 Electro-optic High-speed Switch for Optical Burst Transport Networks

We developed 8 times 8 beam-deflecting optical switch with a switching speed within one microsecond utilizing electro-optic effect of PLZT. A newly-developed radial optical path design and putting-in packaging structure with a monolithic PLC platform were applied.

22.2 A 25Gb/s hybrid integrated silicon photonic transceiver in 28nm CMOS and SOI

Integrated photonic interconnect technology is free from the bandwidth-distance limitation that intrinsically exists in electrical interconnects, promising a disruptive alternative for next-generation scalable data centers. Silicon photonic platforms have been reported based on monolithic and hybrid integration. Monolithic systems mitigate integration overhead but require compromise in either electronic or photonic device performance [1,2]. Hybrid integration allows for independent process selection for each device so that overall system can potentially achieve the best performance [3]. This paper presents a hybrid integrated electrical-optical (E-O) interface including a driver/TIA chip in 28nm CMOS and a modulator/PD chip in SOI, based on a mixed-pitch bumping technology. A pseudo-differential driver with pre-emphasis enables an 800MHz bandwidth (BW) carrier-injection ring modulator to operate at 25Gb/s with power efficiency of 2.9pJ/b. A TIA implements two BW-enhancement techniques: a regulated-cascode (RGC) input stage with shunt-shunt feedback and T-coil inductive peaking, and a hybrid offset calibration, achieving 25Gb/s with power efficiency of 2.0pJ/b and a sensitivity of -8.0dBm OMA.

Development of CPU Package Embedded with Multilayer Thin Film Capacitor for Stabilization of Power Supply

This paper proposes a method of improving power delivery in a CPU package substrate with multilayer thin film capacitors (TFCs). Because TFC embedded technology can reduce the inductance of power delivery path, it can stabilize the power supply to the CPU. Higher permittivity, thinner layer thickness and wider conductor plane area results in larger capacitance. To further stabilize the power supply, we developed a package structure with an embedded double TFC layer that can double the capacitance. The double TFC embedded package was formed by laminating two TFCs to the top and bottom of the core layers in a build–up substrate. Through verification using test vehicles, it was confirmed that electrical performance was significantly improved with the double TFC. Also, it was demonstrated that the criteria of the capacitance and insulation resistance were satisfied in the product reliability tests.

Development of Large Size CPU Package Structure Using Embedded Thin Film Capacitor Package Substrate

This paper reports on a large-size CPU package for UNIX servers which employs embedded thin film capacitor layers. The substrate of this package has two thin film capacitor layers in the surface of the core layer, which has a capacitance of 25 uF in total. In order to adopt this package substrate, we confirmed the effect of the thin film capacitor layers on the package assembly process. We actually measured mechanical characteristics and the coefficient of thermal expansion (CTE), and confirmed that we can use it like conventional package substrates. This package has passed the preprocessing and subsequent environmental test on JEDEC Level 4, and we think that a high-quality package has been developed this time. Fujitsu adopted a low melting point solder BGA from a previous-generation package. Its composition is Sn-57Bi-1.0Ag. However, this solder has an issue with deformation after a low-temperature reflow profile for the solder ball attachment process on the package. In this work, we were able to find the cause of this phenomenon, and by changing the Ag content from 1.0% to 0.4%, we achieved a complete low-temperature assembly process. In addition, BGA connection reliability was confirmed.

Viscoelastic analysis of multistage stacked via structure in build-up substrate

Compact high density electronic equipment is achieved using the stacked via technology in a build-up substrate. In order to design the build-up substrate, the impact of the viscoelasticity behavior of insulating resin under heating and cooling must be considered. This paper investigates how to predict the stacked via fatigue life using a viscoelastic analysis. The thermal cycle test, elastic analysis and the viscoelastic analysis were conducted in eight variations of stacked via structure including either of two resins. Either three, four, five, or six build-up via (BU via) were stacked on the plated-through hole (PTH) in these structures. As a result, the viscoelastic analysis agreed well with that of the thermal cycle test in any stacked via structure.

Electrical characteristics of build-up substrates using new via structures

The electrical characteristics of the power supply path, which are influenced by the via structures in the build-up substrate were investigated. The build-up substrates are composed of core layers and build-up layers, connected by the plated through hole (PTH), and the build-up via (BU via), respectively. This paper investigates how the BU via structures affect the power supply path, and discusses the design constraints of the via structures in the build-up layers. Three design constraints were considered for the build-up substrate, which comprises six build-up layers laminated on both sides of the core layers. The first constraint limits the BU via stack number, the second is the propriety of the BU via stack on the PTH, and the last limits the number of BU vias connected on the PTH. By changing these design constraints, the power supply paths were designed and compared by simulation and measurement. As a result, the proposed via structure significantly reduced the resistance and inductance of the power supply path in the substrate, while yielding good connectivity and productivity.