Dale Jonathan Pearson

Copper Interconnection Integration and Reliability

Abstract A processing sequence to produce a multilevel Cu/polyimide structure which is stable in a corrosive environment is described. Using a combination of dry etching and chemical-mechanical polishing, a fully planarized Cu/polyimide wiring structure was obtained. This technology has been successfully applied to the fabrication of 64 kb complementary metal-oxide-semiconductor static random access memory (CMOS SRAM) chips. Chip functionality was not affected by 12 thermal cycles from 20 to 400 °C. The electromigration activation energy for evaporated Cu, Cu(Mg), Cu(Zr), Cu(Sn) and chemical vapour deposition (CVD) pure Cu was evaluated using a drift velocity technique. The mass transport rates of CVD Cu and evaporated Cu were found to be essentially the same, with an electromigration activation energy of 0.70 ± 0.05 eV. An Mg impurity in Cu enhances the electromigration damage rate in Cu, while Sn and Zr drastically increase the Cu electromigration failure lifetime.

Operational amplifier based test structure for transistor threshold voltage variation

A new test structure has been developed, which is comprised of MOSFET arrays and an on-chip operational amplifier feedback loop for measuring threshold voltage variation. The test structure also includes an on-chip clock generator and address decoders to scan through the arrays. It can be used in an inline test environment to provide rapid assessment of Vt variation for technology development and chip manufacturing. Hardware results in a 65 nm technology are presented.

Operational Amplifier Based Test Structure for Quantifying Transistor Threshold Voltage Variation

A new test structure has been developed, which is comprised of MOSFET arrays and an on-chip operational amplifier feedback loop for measuring threshold voltage variation. The test structure also includes an on-chip clock generator and address decoders to scan through the arrays. It can be used in an inline test environment to provide rapid assessment of Vt variation for technology development and chip manufacturing. Hardware results in a 65-nm technology are presented. The significance of the bias dependence of Vt variation is discussed for SRAM product designs.

High speed test structures for in-line process monitoring and model calibration [CMOS applications]

The use of in-line test structures for routinely monitoring various high frequency aspects of the performance of CMOS gates is described. These compact test structures use DC I/Os and are compatible with standard parametric testers. The specific examples described are ring oscillators for a wide range of self-consistent parameter extraction ranging from circuit delays to gate length and leakage components; and a new class of self-timed/calibrated structure of which a circuit for measuring SOI switching history effects, utilizing 100 ps time-scale self-generated pulses, is presented as a representative example.

Reactive ion etching of Nb/A1Ox/Nb for Josephson technology

Abstract We describe a process for defining and etching Nb/A1Ox/Nb Josephson junctions on 125 mm wafers using standard optical lithographic stencils and low pressure chlorine plasma in a single wafer reactive ion etching tool. The process exhibits selectivities to SiO2 in excess of 10:1 and can be tailored to produce niobium lines with either sloped or vertical profiles. During the etch, the chlorine plasma emission intensity is monitored, providing a distinct signature when etching through the thin AlOx layer and a sharp indication of endpoint as the underlying SiO2 is reached. The etch sequence is programmed to maintain the wafer temperature below 100°C at all times. This process has been used to fabricate a variety of Josephson devices using 2.0 μm groundrules and high quality Josephson junctions as small as 0.5 μm2 in area. In a variation on this process, using direct write electron-beam lithography, we have fabricated niobium features as small as 0.15 μm.

Custom design of CMOS low-power high-performance digital signal-processing macro for hard-disk-drive applications

The design challenges and custom design techniques associated with low-power, smallarea, high-performance CMOS digital signalprocessing circuits for hard-disk-drive applications are presented. The advantages of custom design are demonstrated by an example custom digital FIR filter macro that provides substantial improvement in performance, area, and power dissipation over standard-cell implementations.