Panayotis C. Andricacos

Damascene Copper electroplating for chip interconnections

Damascene Cu electroplating for on-chip metallization, which we conceived and developed in the early 1990s, has been central to IBMs Cu chip interconnection technology. We review here the challenges of filling trenches and vias with Cu without creating a void or seam, and the discovery that electrodeposition can be engineered to give filling performance significantly better than that achievable with conformal step coverage. This attribute of superconformal deposition, which we call superfilling, and its relation to plating additives are discussed, and we present a numerical model that represents the shape-change behavior of this system.

Mechanisms for microstructure evolution in electroplated copper thin films near room temperature

We present a model which accounts for the dramatic evolution in the microstructure of electroplated copper thin films near room temperature. Microstructure evolution occurs during a transient period of hours following deposition, and includes an increase in grain size, changes in preferred crystallographic texture, and decreases in resistivity, hardness, and compressive stress. The model is based on grain boundary energy in the fine-grained as-deposited films providing the underlying energy density which drives abnormal grain growth. As the grain size increases from the as-deposited value of 0.05–0.1 μm up to several microns, the model predicts a decreasing grain boundary contribution to electron scattering which allows the resistivity to decrease by tens of a percent to near-bulk values, as is observed. Concurrently, as the volume of the dilute grain boundary regions decreases, the stress is shown to change in the tensile direction by tens of a mega pascal, consistent with the measured values. The small ...

Electrochemical Fabrication of Mechanically Robust PbSn C4 Interconnections

Electrochemical fabrication of PbSn C4s (controlled collapse chip connection) offers significant cost, reliability, and environmental advantages over the currently employed evaporation technology. A continuous seed layer is required for through-mask electrodeposition of the solder alloy. This layer becomes the ball limiting metallurgy (BLM) for the solder pad after etching. The seed layer metallurgy and the BLM etching are crucial to obtaining mechanically robust C4s. In the present study, the issues related to the selection of seed layer metallurgy, uniformity of plating and etching, and mechanical integrity of C4s have been investigated. The results demonstrate the feasibility of electrochemically fabricating highly reliable PbSn (97/3) C4 structures with a high degree of dimensional uniformity on a variety of wafer sizes ranging up to 200 mm.

Pb-free solder alloys for flip chip applications

In addition to the environmental issue regarding the use of Pb-bearing solders in microelectronics applications, there is another issue associated with using Pb-bearing solders in interconnections, like flip chip solder interconnections in an advanced CMOS technology, that are near active circuits. In order to minimize the soft error rate due to alpha particle emission from Pb-bearing solder alloys, Pb-free solder alloys were studied as possible replacements for the Pb-based solders that are presently used in flip chip interconnections. A large number of solder compositions was selected for evaluation. Since all the candidate alloys were Sn-based, alternatives for the ball-limiting metallurgy (BLM) were also investigated. The physical, chemical, mechanical and electrical properties of the alloys were determined by thermal analysis, wettability testing, microhardness measurement, electrical resistivity measurement, interfacial reaction study and others. Test vehicles were also built with some selected Pb-free solder alloys with the proper BLM to evaluate integrity of the flip chip solder bump structure. Based on this study, a few candidate solder alloys were selected with a proper BLM barrier layer for flip chip applications.

Alloying of a Less Noble Metal in Electrodeposited Cu Through Underpotential Deposition

Underpotential deposition of Pb or Sn on Cu can be used to produce electroplated Cu-Pb and Cu-Sn alloys, with small amounts of alloyed Pb and Sn, from acid solutions that do not contain complexants. Such alloys are of interest as possible on-chip wiring for very large scale integration ; the content of alloying agent must be kept small in order to maintain a low resistivity. The primary requirement for the formation of the alloys is that the deposition process occur in the range of underpotential deposition (UPD) ; this requirement can be met in solutions of methane sulfonic acid (MSA). Both Pb(II) and Sn(II) depolarize Cu deposition from MSA ; the Sn(II) is the weaker depolarizer. Thus, in the absence of other additions to the Cu(II)/MSA solution, electrodeposition proceeds in the UPD range in the presence of Pb(II), producing a Cu-Pb alloy, but positive to the UPD range in the presence of Sn(II), producing pure Cu. The deposition potential can be manipulated by addition agents in solution. A direct relationship exists between the potential and the amount of incorporated Pb or Sn for all solution compositions and plating conditions, provided that the solution does not contain strongly adsorbing species that interfere with the UPD process. The minor component has been shown to be incorporated in the metallic state, even though the deposition potential is positive to its reversible potential.

Determination of Partial Currents for CuNi and CuCo Electrodeposition Using Rotating Ring‐Disk Electrodes

An electrochemical stripping technique has been developed for the analysis of Cu alloys with iron-group metals (particularly Ni). The alloy is plated on the disk of a rotating ring-disk electrode. The electrode is transferred after plating to an HCl solution and stripped potentiodynamically

Characterization of Plated Cu Thin Film Microstructures

Electroplated Cu was found to have a fine as-plated microstructure, 0.05 ±0.03 μm, with multiple grains through the film thickness and evidence of twins and dislocations within grains. Over time at room temperature, the grains grew to greater than 1 μ m in size. Studied as a function of annealing temperature, the recrystallized grains were shown to be 1.6 ± 1.0 μ m in size, columnar and highly twinned. The grain growth was directly related to the time dependent decrease in sheet resistance. The initial grain structure was characterized using scanning transmission electron microscopy (STEM) from a cross-section sample prepared by a novel focused ion beam (FIB) and lift-out technique. The recrystallized grain structures were imaged using FIB secondary electron imaging. From these micrographs, the grain boundary structures were traced, and an image analysis program was used to measure the grain areas. A Gaussian fit of the log-normal distribution of grain areas was used to calculate the mean area and standard deviation. These values were converted to grain size diameters by assuming a circular grain geometry.

Study of field‐driven wall‐configuration conversions for laminated Permalloy in the easy‐axis state

Laminated Permalloy, with edge‐curling walls replacing closure domains, has been proposed to increase permeability and reduce wall noise in recording. However, in structures meeting the criteria for Slonczewski’s ‘‘easy‐axis’’ state, normal walls often coexist with edge‐curling walls. We have used our laser magneto‐optic microscope to study inductive‐head‐yoke shaped elements of two and four Permalloy layers separated by nonmagnetic, metallic spacers. In the four‐magnetic‐layer sample a state with a single wall, terminating at the edge‐curling regions and lying along the easy‐axis direction, is often observed on the top and bottom layers. Some elements may be driven into an easy‐axis state with no observed domain walls. The two‐magnetic‐layer sample also exhibited simultaneous one‐wall structures on the top and bottom layers. The other stable configuration was a no‐wall state on the top layer and a two‐wall (three‐domain) state on the lower layer. These ‘‘coupled’’ states were exceptionally stable in both...

Fabrication challenges for next-generation devices: Microelectromechanical systems for radio-frequency wireless communications

With wireless communications becoming an important technology and growth engine for the semiconductor industry, many semiconductor companies are developing technologies to differentiate themselves in this area. One means of accomplishing this goal is to find a way to integrate passive components, which currently make up more than 70% of the discrete components in a wireless handset, directly on-chip thereby greatly simplifying handsets. While a number of technologies are being investigated to allow on-chip integration, microelectromechanical systems technologies are an important part of this development effort. They have been used to create switches, filters, local oscillators, variable capacitors, and high-quality inductors, to name a few examples. The lithography requirements for these devices are very different than those found in standard semiconductor fabrication with the most important involving patterning over extreme topography. We discuss some of the fabrication challenges for these devices as well as some approaches that have been demonstrated to satisfy them.

Behavior of Cu ( P ) and Oxygen Free High Conductivity Cu Anodes under Electrodeposition Conditions

Research was carried out in part at beamline X23A2 at the National Synchrotron Light Source, Brookhaven National Laboratory, which is supported by the U.S. Department of Energy, Division of Materials Sciences and Division of Chemical Sciences. H.S.I. was supported by the U.S. Department of Energy, Division of Materials Sciences, Office of Basic Energy Science under Contract No. DE-AC02-76CH00016.