Manjul Bhushan

Ring oscillator based technique for measuring variability statistics

Device parameter induced frequency variations in a dense array of nominally identical ring oscillators are measured by sequentially combining the output frequencies into a single frequency modulated signal with the statistical frequency parameters read out by a standard frequency counter. For the example described here, the ring oscillators are designed to capture random variations in MOSFET threshold voltages.

Product-representative At speed test structures for CMOS characterization

The design of product-representative test structures for measuring and characterizing CMOS circuit performance, power, and variability at speeds characteristic of present-day microprocessors is described. The current use of this set of test structures in the IBM partially depleted silicon-on-insulator CMOS technologies covers diagnostics in early process development, monitoring mature processes in manufacturing, enabling model-to-hardware correlation, and tracking product performance. The designs focus on measuring high-frequency performance early in the product fabrication cycle while minimizing test and data analysis time. The physical layouts are compact, facilitating placement in the chip. A subset of these test structures can be measured at the first metal level, while more complex designs use three or more metal layers. Most designs are compatible with standard in-line parametric test equipment, although a limited number of bench tests continue to play an important role. Differential measurement techniques are key to many of the test structure designs. Hardware data analysis also relies heavily on differencing schemes for relating MOSFET parameters and associated parasitic components to circuit delays in a self-consistent manner.

Ring Oscillator Based Test Structure for NBTI Analysis

We have developed a new NBTI test structure comprising differential pairs of ring oscillators with stages of various circuit types. For stages consisting of inverters driving p-FET passgates, the gates of which are set at an adjustable DC potential, this structure allows high resolution absolute measurement of the average Vt shift of a large number (~ 100) product representative p-FETs in response to very short as well as traditional long duration pure NBTI AC or DC voltage/temperature stresses.

Data Analysis Techniques for CMOS Technology Characterization and Product Impact Assessment

A methodology based on canonical views is developed to facilitate rapid analysis of CMOS characterization and test data for product and process debug. The compressed representations aid in both quantitative and intuitive assimilation of the data, with a focus on model-to-hardware correlation and manufacturing variability

Photon emission microscopy of inter/intra chip device performance variations

We propose a simple, noninvasive, optical technique to measure intra-wafer and intra-chip MOSFET performance variations. Technique utilizes correlation between device performance and weak near-infrared emission from its off-state current. It maps performance variations, producing quantitative data. We experimentally demonstrate our technique on 130 nm SOI microprocessor.

Circuit and technique for characterizing switching delay history effects in silicon-on-insulator logic gates

The delay of a partially depleted silicon-on-insulator complementary metal oxide semiconductor (MOS) logic gate can vary by 10% or more due to history effects. We describe and demonstrate a circuit and measurement technique with which one can measure history effects dominated by either the output rising (pMOS) or output falling (nMOS) characteristics of a multiple-input silicon-on-insulator gate. To precondition the floating-body voltages, any combination of inputs and number of switching events, arbitrarily configured with respect to timing and sequence, may precede an event to be measured.

CMOS latch metastability characterization at the 65-nm-technology node

A new test structure utilizing a differential technique for measuring CMOS latch delay with sub-ps time resolution is described. The latch delay and error count in the metastability region are measured as a function of clock-data delay which can be incremented in 0.1 ps steps. This compact test structure is configured to be placed in the scribe line for characterizing different latch designs and correlating their behavior with model predictions.

Generation, elimination and utilization of harmonics in ring oscillators

Higher frequency harmonics in ring oscillators are problematic in both data acquisition and analysis. The origin of these undesirable harmonics and a circuit scheme for effectively eliminating them are described. Controlled generation of higher harmonics, on the other hand, enables unique applications in determining circuit power performance trade-offs.

Addressable Arrays Implemented with One Metal Level for MOSFET and Resistor Variability Characterization

Addressable array test structures for rapid collection of statistical distributions of MOSFET parameters and parasitic resistances are described. A unique feature of these designs is that they require only one level of metal, yet are compact for placement in the scribe line for early process learning. MOSFET measurements are made over full range of I-V characteristics including leakage currents of individual devices in the sub-threshold region. A modular approach for test structure integration and parallel testability enables high efficiency in design and data acquisition.

High speed test structures for in-line process monitoring and model calibration [CMOS applications]

The use of in-line test structures for routinely monitoring various high frequency aspects of the performance of CMOS gates is described. These compact test structures use DC I/Os and are compatible with standard parametric testers. The specific examples described are ring oscillators for a wide range of self-consistent parameter extraction ranging from circuit delays to gate length and leakage components; and a new class of self-timed/calibrated structure of which a circuit for measuring SOI switching history effects, utilizing 100 ps time-scale self-generated pulses, is presented as a representative example.