Brian L. Ji

Practical Strategies for Power-Efficient Computing Technologies

After decades of continuous scaling, further advancement of silicon microelectronics across the entire spectrum of computing applications is today limited by power dissipation. While the trade-off between power and performance is well-recognized, most recent studies focus on the extreme ends of this balance. By concentrating instead on an intermediate range, an ~ 8× improvement in power efficiency can be attained without system performance loss in parallelizable applications-those in which such efficiency is most critical. It is argued that power-efficient hardware is fundamentally limited by voltage scaling, which can be achieved only by blurring the boundaries between devices, circuits, and systems and cannot be realized by addressing any one area alone. By simultaneously considering all three perspectives, the major issues involved in improving power efficiency in light of performance and area constraints are identified. Solutions for the critical elements of a practical computing system are discussed, including the underlying logic device, associated cache memory, off-chip interconnect, and power delivery system. The IBM Blue Gene system is then presented as a case study to exemplify several proposed directions. Going forward, further power reduction may demand radical changes in device technologies and computer architecture; hence, a few such promising methods are briefly considered.

A fully-integrated switched-capacitor 2∶1 voltage converter with regulation capability and 90% efficiency at 2.3A/mm 2

A switched-capacitor DC-DC voltage converter in 45nm SOI CMOS leverages on-chip trench capacitors to achieve 90% efficiency at an output of 2.3A/mm2 for 2V-to-0.95V conversion at 100MHz. Operation in step-up and step-down modes is demonstrated. Combined with stacked voltage domains, self-regulation capability enables further efficiency improvement.

Operational amplifier based test structure for transistor threshold voltage variation

A new test structure has been developed, which is comprised of MOSFET arrays and an on-chip operational amplifier feedback loop for measuring threshold voltage variation. The test structure also includes an on-chip clock generator and address decoders to scan through the arrays. It can be used in an inline test environment to provide rapid assessment of Vt variation for technology development and chip manufacturing. Hardware results in a 65 nm technology are presented.

Operational Amplifier Based Test Structure for Quantifying Transistor Threshold Voltage Variation

A new test structure has been developed, which is comprised of MOSFET arrays and an on-chip operational amplifier feedback loop for measuring threshold voltage variation. The test structure also includes an on-chip clock generator and address decoders to scan through the arrays. It can be used in an inline test environment to provide rapid assessment of Vt variation for technology development and chip manufacturing. Hardware results in a 65-nm technology are presented. The significance of the bias dependence of Vt variation is discussed for SRAM product designs.

Destructive-read random access memory system buffered with destructive-read memory cache for SoC applications

This paper describes a novel random access memory system. The system is based on a destructive-read memory buffered by a destructive-read memory cache for hidden write back. SRAM comparable random access cycle time (tRC) is achieved, as tRC of the architecture is limited only by the destructive-read time of the memory array. By using a DRAM array as cache, the silicon area is reduced by about 25% from SRAM-cache system. Write back algorithms have been proved by mathematical models, and confirmed by simulations.

On the Connection of SRAM Cell Stability with Switching History in Partially Depleted SOI Technology

Read and write operational margins for SRAM cells in partially depleted silicon on insulator (PD-SOI) technology are studied. In both simulation and concept, cell stability is shown to be directly connected to the inverter nFET first switch/second switch history, thus linking SRAM margins to a PD SOI parameter that can be measured and monitored