Damien Lenoble

Silicon-on-Nothing (SON)-an innovative process for advanced CMOS

A novel CMOS device architecture called silicon on nothing (SON) is proposed, which allows extremely thin (in the order of a few nanometers) buried dielectrics and silicon films to be fabricated with high resolution and uniformity guaranteed by epitaxial process. The SON process allows the buried dielectric (which may be an oxide but also an-air gap) to be fabricated locally in dedicated parts of the chip, which may present advantages in terms of cost and facility of system-on-chip integration. The SON stack itself is physically confined to the under-gate-plus-spacer area of a device, thus enabling extremely shallow and highly doped extensions, while leaving the HDD (highly doped drain) junctions comfortably deep. Therefore, SON embodies the ideal device architecture taking the best elements from both bulk and SOI and getting rid of their drawbacks. According to simulation results, SON enable ables excellent Ion/Ioff trade-off, suppressed self-heating, low S/D series resistance, close to ideal subthreshold slope, and high immunity to SCE and DIBL down to ultimate device dimensions of 30 to 50 nm.

Multi-gate devices for the 32nm technology node and beyond

Due to the limited control of the short channel effects, the high junction leakage caused by band-to-band tunneling and the dramatically increased VT statistical fluctuations, the scaling of planar bulk MOSFETs becomes more and more problematic with every technology node. The ITRS roadmap predicts that from the 32 nm technology node on planar bulk devices will not be able to meet the stringent leakage requirements anymore and that multi-gate devices will be required. In this paper, the suitability of FinFET based multi-gate devices for the 32 nm technology and beyond will be discussed. Apart from the benefits, some technological challenges will be addressed.

Investigation of fully- and partially-depleted self-aligned SiGeC HBTs on thin film SOI

This paper presents a comprehensive experimental study of the static and dynamic characteristics of self-aligned vertical SiGeC HBTs fabricated on CMOS compatible, thin film SOI substrates. In particular, the influence of collector doping and layout on the performance of fully-depleted transistors is described in details. The potentiality of partially-depleted SOI HBTs for high speed applications is also demonstrated, with cut-off frequencies f/sub T/= 102GHz and f/sub MAX/= 154GHz reported here for the first time.

Integration and optimisation of a high performance RF lateral DMOS in an advanced BiCMOS technology

In this paper, we present the optimisation of a RF lateral DMOS and its integration in an advanced 0.25 /spl mu/m SiGe:C BiCMOS technology. The proposed device shows excellent characteristics; Ron is around 2.5 /spl Omega/.mm with a BVDS larger than 13 V, f/sub T/ and F/sub max/ reach 21 GHz and 40 GHz respectively. These performances fit wireless RF-power amplifier needs. Integration of such a device in a RF oriented BiCMOS process is a key issue for a SOC approach of wireless circuits.

Evaluation of wet-developable KrF organic BARC to improve CD uniformity for implant application

As integrated circuit manufacturing moves towards smaller feature sizes, ion implant photo levels are becoming critical layers with lithography demands as tight as 180 nm line/space patterning capability. Advanced materials are required for junction levels to improve the critical dimension (CD) control and resolution. Dyed KrF resists are reaching the limit in their ability to control CD variation due to parasitic light reflections from the underlayer. The use of a bottom anti-reflective coating (BARC) under KrF resists reduces the reflective effect from the oxide substrate, leading to better CD control. Unfortunately, a standard organic BARC that requires plasma etch before implantation can cause silicon substrate oxidation damage as well as increased wafer cost due to additional process steps. The use of a new developer-soluble organic BARC shows an advantage in optics without degrading the underlying substrate before implantation. The advantage of using an ESCAP resist in combination with a wet-developable BARC over the single resist layer scheme has been clearly demonstrated and the system is well adapted to ion implant layers for 65 nm technology.

MUGFET - alternative transistor architecture for 32 nm CMOS generation

In this paper, the suitability of the MUGFET technology as an alternative device architecture for 32 nm CMOS generation is discussed. In particular, the requirements for the MUGFET devices with focus on FIN geometry, gate stack, and junctions are analyzed. Technological challenges related to the processing of MUGFET devices such as, FIN and gate patterning, junctions and spacer formation, are also presented

Selective SiGe Etching Formed by Localized Ge Implantation on SOI

The fully depleted SOI devices present lateral isolation issues due to the shallow trench isolation (STI) process. We propose in this paper to study a new fabrication process for integrating local isolation trenches. Germanium (Ge) implantation is used to create SiGe (Silicon-Germanium) layer on thin SOI (silicon on insulator) that can be selectively etched. The advantage is the capability of implantation to localize the SiGe area on this substrate and to avoid STI process issues. Aggressive dimensions and geometries are studied and resulting material transformation (crystallization and Ge diffusion) are apprehending via SEM (Secondary Electron Microscopy) or AFM (Atomic Force Spectroscopy) to understand the etching kinetics. After optimization, we demonstrate the capability of fabricating localized trenches on SOI without degrading the neighboring Si layer or consuming the thin BOX (buried oxide).

Suppression of boron transient-enhanced diffusion in SiGe HBTs by a buried carbon layer

The experiments described in this paper show that base broadening effects due to extrinsic base implantation in SiGe HBTs can be suppressed by introducing a buried carbon layer under the SiGe/Si base prior to epitaxy. They also demonstrate that SiGe HBTs with excellent static (/spl beta//spl times/V/sub AF//spl sim/10/sup 4/ V) and dynamic (f/sub T/B/spl times/BV/sub CEO//spl sim/200 GHz/spl times/V) characteristics can be fabricated using an epitaxially aligned in-situ-doped polysilicon emitter and an appropriately designed SiGe/Si base profile.