Nak-Jin Son

Multi-gate devices for the 32nm technology node and beyond

Due to the limited control of the short channel effects, the high junction leakage caused by band-to-band tunneling and the dramatically increased VT statistical fluctuations, the scaling of planar bulk MOSFETs becomes more and more problematic with every technology node. The ITRS roadmap predicts that from the 32 nm technology node on planar bulk devices will not be able to meet the stringent leakage requirements anymore and that multi-gate devices will be required. In this paper, the suitability of FinFET based multi-gate devices for the 32 nm technology and beyond will be discussed. Apart from the benefits, some technological challenges will be addressed.

Flexible and robust capping-metal gate integration technology enabling multiple-VT CMOS in MuGFETs

We report, for the first time, a comprehensive study on various capping integration options for WF engineering in MuGFET devices with TiN gate electrode: HfSiO/cap/TiN, cap/HfSiO/TiN and HfSiO/TiN/cap/TiN vs. reference deposition sequence HfSiO/TiN (cap = Al2O3 for pmos, and Dy2O3 or La2O3 for nmos). We show that: 1) low-VT values (Lt 0.3 V) are achieved for both nmos and pmos, with excellent process control and device behavior down to Lg ap 50 nm and WFIN ap 20 nm, for optimized gate stack configurations; 2) inserting a cap layer in-between TiN layers instead of HfSiO/cap/TiN leads to improved mobility, reduced CET without impacting JG, similar noise response and improved BTI behavior, with correction of the abnormal PBTI degradation seen for HfSiO/DyO/TiN. Is also enables simplified and more robust CMOS co-integration of low- and med-VT devices in the same wafer, avoiding loss in CET and damage of the host dielectric with the cap removal process.

A unique dual-poly gate technology for 1.2-V mobile DRAM with simple in situ n/sup +/-doped polysilicon

Highly manufacturable sub-100-nm 1.2-V mobile dynamic random access memory (DRAM) having full functionality and excellent reliability have been successfully developed. A unique and simple DRAM technology with dual-gate CMOSFET was realized using plasma-nitrided thin gate oxide and p/sup +/ poly gate formed by BF/sub 2/ ion implanted compensation of in situ phosphorus (n/sup +/) doped amorphous silicon gate. Using this technology, boron penetration into the channel, gate poly depletion, and dopant interdiffusion between n/sup +/- and p/sup +/-doped WSi/sub x/-polycide gates were successfully suppressed. In addition, a negatively biased word line scheme and a storage capacitor with laminated high-/spl kappa/ Al/sub 2/O/sub 3/ and HfO/sub 2/ dielectrics were also developed to achieve mobile DRAM operating at 1.2 V with excellent performance and reliability.

MUGFET - alternative transistor architecture for 32 nm CMOS generation

In this paper, the suitability of the MUGFET technology as an alternative device architecture for 32 nm CMOS generation is discussed. In particular, the requirements for the MUGFET devices with focus on FIN geometry, gate stack, and junctions are analyzed. Technological challenges related to the processing of MUGFET devices such as, FIN and gate patterning, junctions and spacer formation, are also presented

Drain leakage fluctuation reduction in the recessed channel array transistor DRAM with the elevated source-drain

Gate induced drain leakage (GIDL) characteristics were investigated with the recessed channel array transistor (RCAT) for DRAM, using the elevated source drain (ESD). The lower doping concentration of a source-drain region in the ESD structure reduces the electric field, which reduces drain leakage current and also the fluctuation of leakage current. These reductions can enhance the data retention time of DRAM. The reduced electric field also improves hot carrier immunity of the cell transistor as well.

Effects of RTA and WSi/sub x/-polycide gate processes on MOSFET reliability for giga-bit scale DRAMs

We report the process effects on the MOSFET reliability and characteristics for the gate stack formation process in DRAM (Dynamic Random Access Memory). A rapid thermal annealing (RTA) process, employed for the reduction of word-line resistance and the improvement of hot-carrier life-time, caused an increase of the gate-induced drain leakage (GIDL) current. WSi/sub x/ gate dependence, Hot-Carrier (HC) and Fowler-Nordheim (FN) stress effects are also studied.