Pascal Ribot

Dielectric pockets-a new concept of the junctions for deca-nanometric CMOS devices

A new concept of dielectric pockets is proposed allowing suppression of short-channel effects (SCEs) and DIBL without increasing the channel doping. The dielectric pockets have been implanted into 0.15-/spl mu/m PMOS devices showing substantial efficiency in reducing SCE and I/sub OFF/ current without altering the current drive. The dielectric pockets thus embody the ideal pocket architecture.

A high-speed low 1/f noise SiGe HBT technology using epitaxially-aligned polysilicon emitters

A 200 mm 0.35 /spl mu/m silicon-germanium heterojunction bipolar transistor (SiGe HBT) technology involving epitaxially-aligned polysilicon emitters is described. The devices are shown to combine the high speed performances typical for poly-Si emitter SiGe base devices (f/sub max/ up to 70 GHz) and the low 1/f noise properties of monocrystalline emitter structures (noise figure-of-merit KB as low as 7.2/spl times/10/sup -10/ /spl mu/m/sup 2/). Statistical current gain data are used to demonstrate the manufacturability of this innovative SiGe HBT technology.

Dielectric pockets – a new concept of the junctions for deca-nanometric CMOS devices

A new concept of dielectric pockets is proposed allowing suppression of short-channel effects (SCEs) and DIBL without increasing the channel doping. The dielectric pockets have been implanted into 0.15- m PMOS devices showing substantial efficiency in reducing SCE and current without altering the current drive. The dielectric pockets thus embody the ideal pocket architecture.

Low-temperature selective epitaxy of silicon with chlorinated chemistry by RTCVD

Low-temperature epitaxial depositions are greatly attractive in the way of device fabrication, in order to improve electrical performances of advanced complementary metal oxide semiconductor (CMOS) and BiCMOS technologies. They present, however, some important difficulties such as a very high sensitivity to temperature and complex loading effects. In this paper, we investigate the selective epitaxy of silicon based on the dichlorosilane (DCS)/HCl/H 2 chemistry using an industrial 200-mm single wafer chemical vapour deposition at reduced pressure (< 40 Torr) and low temperature (700-900 °C). First, we use a new evaluation procedure of the selectivity of Si epitaxy processes on thin nitride and oxide blanket coverage wafers with very low nuclei density counted with a surfscan. We evaluate the effects of intrinsic parameters of deposition such as HCl partial pressure and a parameter rarely reported in the literature: the duration of processes. Then we present results about global loading effects of Si growth within the DCS/H 2 system and of Si etch within the HCl/H 2 system. This allows us to anticipate and to give a new interpretation of the DCS/HCl/H 2 system loading effects. Special attention has been taken in order to eliminate the thermal contribution of different substrates and only chemical loading effects are reported. These studies are relevant to the fabrication of elevated source and drain, which have been integrated in an industrial CMOS technology.

Selective SiGe epitaxy by rtcvd for new device architectures

CMOS technologies and devices are approaching their theoretical limits such as optical lithography, gate oxide thickness, etc. Consequently, new efforts are made in order to improve or modify device architecture. New epitaxial films grown at low temperature have potential of improving both electrical performances and integration of advanced devices. Firstly, we investigate the selective SiGe epitaxy with high Ge content based on the DCS/GeH 4 /HCl/H 2 chemistry using an industrial 200 mm single wafer chemical vapour deposition at reduced pressure ( < 40 Torr) and low temperature (600-750 °C). We present new results about global loading effects in terms of growth and Ge content (15-40%) of perfectly strained SiGe films used for their selective etch properties in new device architectures. Secondly, we report on morphological results of the novel CMOS device architecture called silicon-on-nothing (SON). They allow extremely thin (a few nanometers) buried dielectric and silicon films to be fabricated with high resolution and uniformity guaranteed by SiGe and Si selective epitaxial processes. It is a very permissive structure as first approach of ultra thin SOI films.

Investigations on Poly-SiGe Gate in Full 0.1um CMOS Integration

CMOS transistors down to 0.1µm gate length were successfully fabricated with polySiGe gate. Various germanium fractions (<25%) were investigated coupled with different gate doping impurities. We show that Arsenic can reduce the benefit of polySiGe in terms of dopant activation in the gate. However, we demonstrated that an optimum germanium fraction (20%) can reduce polydepletion in both nMOS and pMOS transistors. We also examined on the impact of polySiGe on the gate oxide reliability, showing that the oxide lifetime of devices integrated with a polySiGe electrode has been improved.

Optimized Si/SiGe notched gates for CMOS

The process developed here uses the wellcontrolled and highly selective etching between Poly-SiGe and Poly-Si in a downstream plasma equipment for processing notched-gate devices. Two notch length, 15 and 30 nm, were processed. The optimum was clearly evidenced for the shortest notch (15 nm), in terms of performance and gate current reduction (at low field). For this notch length, no degradation in SCE and at the same time a slight improvement in Gmsat was measured in comparison with standard transistors. In addition, a reduction of poly-depletion due to a better activation of dopants in SiGe in both NMOS and PMOS gates has been measured.

Suppression of boron transient-enhanced diffusion in SiGe HBTs by a buried carbon layer

The experiments described in this paper show that base broadening effects due to extrinsic base implantation in SiGe HBTs can be suppressed by introducing a buried carbon layer under the SiGe/Si base prior to epitaxy. They also demonstrate that SiGe HBTs with excellent static (/spl beta//spl times/V/sub AF//spl sim/10/sup 4/ V) and dynamic (f/sub T/B/spl times/BV/sub CEO//spl sim/200 GHz/spl times/V) characteristics can be fabricated using an epitaxially aligned in-situ-doped polysilicon emitter and an appropriately designed SiGe/Si base profile.