Robin Cerutti

Unexpected mobility degradation for very short devices : A new challenge for CMOS scaling

A new mobility degradation specific to short channel MOSFETs is studied and elucidated. Pocket implants/dopants pile-up, interface states/oxide charges, remote Coulomb scattering or ballisticity are insufficient to explain this degradation. The role of non-Coulombian (neutral) defects, which can be healed by increasing the annealing temperature, is evidenced

Highly performant double gate MOSFET realized with SON process

Utilizing the SON (silicon on nothing) process, highly performant double gate devices have been processed in a planar configuration. Two families of devices were obtained (high performance and low power) with very high Ion/Ioff trade off. Drive currents of 1954 /spl mu/A//spl mu/m (Ioff = 283 nA//spl mu/m) and 1333 /spl mu/A//spl mu/m (Ioff = 1 nA//spl mu/m) are obtained at 1.2 V with Tox = 20 /spl Aring/ and Lgate = 70 nm. DIBL is very well controlled, measured below 60 mV for gates as short as 40 nm. These features place our devices among the most performant ever reported.

Poly-gate replacement through contact hole (PRETCH): a new method for high-k/metal gate and multi-oxide implementation on chip

We report on a new concept for an easy co-integration, on a same chip, of different MOSFET configurations (GP, LP, HS, buffer transistors) realized after the end of the standard FE process. This poly-gate replacement through contact hole (PRETCH) concept enables replacement of initial poly-silicon gate and/or gate oxide by any gate stack desired. PRETCH addresses multi-Vt control, multi-oxide realization and metal gate integration challenges. As PRETCH gate replacement takes place after PMD (beginning of BE), it is perfectly suitable for high-K integration, allowing low thermal budget (no source and drain anneal seen by HK) and no particular contamination issues. Large potential of PRETCH integration is confirmed by promising morphological results and by very good electrical characteristics of both nMOS and pMOS TiN 90nm gate length MOSFETs. Integration of TiN gate with three different oxide configurations is demonstrated: initial thermal oxide left, replaced by either slot plane antenna [SPA] oxide or high-K. PRETCH concept has also been validated on 3D architectures such as DG. Finally, functional TiN DG inverters and SRAMs are demonstrated.

Compact Modeling of Symmetrical Double-Gate MOSFETs Including Carrier Confinement and Short-Channel Effects

A compact model for the drain current and node charges in symmetrical Double-Gate (DG) MOSFET, including short-channel and carrier confinement effects is developed. The model is particularly well adapted to ultra-scaled devices, with short-channel lengths and ultra-thin silicon films. An extensive comparison step with 2D quantum numerical simulation fully validates the model. The model is also shown to reproduce with an excellent accuracy experimental drain current measured in DG devices fabricated with Silicon-on-Nothing (SON) process. Finally, the DG model has been successfully implemented in Eldo IC analog simulator, demonstrating the application of the model to circuit simulation.

Highly performant double gate MOSFET realized with SON process: how we address the design and process for the GAA SON challenges ?

Utilizing the SON (Silicon On Nothing) process, highly performant double gate devices have been processed in a planar configuration. Two families of devices were obtained (High Performance and Low Power) with very high Ion/Ioff trade off. Drive currents of 1954/spl mu/A//spl mu/m (Ioff = 283 nA//spl mu/m) and 1333/spl mu/A//spl mu/m (Ioff = 1 nA//spl mu/m) are obtained @1.2V with Tox = 20A and Lgate = 70nm. DIBL is very well controlled, measured below 60mV for gates as short as 40nm. These features place our devices among the most performant ever reported. After this GAA planar device demonstration, we are looking for his optimization in consideration of the future technologic node challenges: We define a new architecture for GAA and DG device in order to minimize the overlap capacitance, to use a SOI substrate and to create a GAA circuit with the same layout density than bulk. We develop a new concept of Metal gate and/or High-K integration in MOSFET: the PRETCH (Poly Replacement Through Contact Hole) to allow the best compromise between the mobility, and the Vt adjust for the future device generation. The first demonstration of the PRETCH integration was done on bulk CMOS.

Measurement of Capacitances in Multigate Transistors by Coulomb Blockade Spectroscopy

The occurence of periodic Coulomb blockade in transistors at low temperature allows to extract the capacitances between the channel and the gate, source, and drain. This extremely sensitive method is well adapted to nanoscale devices, where these capacitances are well below the fF range and in parallel with low resistances. We applied this method to 3-D stacked MOSFETs featuring a double-gate top channel and a single-gate bottom channel. The measured gate capacitances are in excellent agreement with estimations based on the geometry, and are independent on the gate voltage. The source and drain capacitances can also be measured separately for each parallel conduction channel, even when their values are markedly different. We illustrate this case with a device with one dominating double-gate channel and a buried, single-gate channel which is not detectable at 300 K and contributes for less than 5% to the total conductance at 4.2 K.

Metal gate-all-around CMOS integration using poly-gate replacement through contact hole (PRETCH)

In this paper, the authors presented an integration strategy for metal gate GAA transistors made by SON process using poly-gate replacement through contact hole (PRETCH). Double gate (DG) type MOSFETs, including planar DG gate-all-around and fin-FETs are today known as the best candidates for the ultimate sealing of the logic CMOS technologies on silicon. One of the main difficulties in optimizing DG devices is the control of the threshold voltage (V/sub th/) from high performances to low power devices. With polysilicon gates, a higher channel doping has to be used when lowering the silicon thickness (T/sub Si/). This adjustment strategy has its limits and thus, gate workfunction engineering seems necessary for thin DG transistors.