Daniel Arbet

New OBIST Using On-Chip Compensation of Process Variations Toward Increasing Fault Detectability in Analog ICs

A new on-chip oscillation test strategy for analog and mixed-signal circuits is presented. In the proposed method, onchip Schmitt trigger is used as the on-chip frequency reference to compensate the influence of process parameter variations. Furthermore, this solution also brings the possibility to implement Oscillation-based Built-In Self-Test (OBIST) for analog and mixed-signal integrated circuits. The proposed OBIST strategy has been experimentally applied to active analog integrated filters, and its efficiency in detecting hard-detectable catastrophic faults is presented. To demonstrate applicability of the proposed method also in nanoscale technologies, the method has been used to test a noninverting amplifier designed in 90 nm CMOS technology. Consequently, the impact of scaling was analyzed and the method efficiency in covering catastrophic faults achieved for 0.35 μm and 90 nm CMOS technology were compared.

Increasing the efficiency of analog OBIST using on-chip compensation of technology variations

A new strategy for on-chip test of an operational amplifier as a part of complex analog and mixed-signal systems is described. During test mode, the operational amplifier is disconnected from the rest of the circuit and transformed to an oscillator. To evaluate the circuit, its oscillation frequency is then compared to a frequency given by a Schmitt trigger oscillator, used as the on-chip reference to compensate technology variations. This method might bring a possibility to implement the Oscillation-based Built-In Self-Test (OBIST) for operational amplifiers as a part of complex systems.

Application of I DDT test towards increasing SRAM reliability in nanometer technologies

Dynamic supply current test method (IDDT test) in static random access memory (SRAM) cell arrays is addressed in order to unveil weak open defects. Simulations were carried out on a 64-bit SRAM circuit, where several parameters of the IDDT waveform were monitored. The SRAM circuit was designed in a 90 nm CMOS technology. Efficiency of IDDT test in unveiling open defects was evaluated and the achieved results were compared for four SRAM arrays with cells of different cell ratio (CR). Moreover, a solution for transformation of the dynamic current to voltage is presented. After the transformation of the current waveform to a voltage waveform, the parameters of the voltage waveform similar to those of the current waveform are easily monitored and evaluated.

Digital methods of offset compensation in 90nm CMOS operational amplifiers

This paper deals with comparison of two discrete methods for digital trimming of the input offset voltage in operation amplifiers designed in 90nm CMOS technology. Two different topologies based on the binary weighed ladder, one using successive approximation register (SAR) and the other employing a simple counter, were compared. Furthermore, a correction circuit was proposed and used to form the mean offset voltage and increase the probability that its value after trimming process will be near zero. Finally, achieved results and improvements are discussed.

Efficiency of oscillation-based BIST in 90nm CMOS active analog filters

Research presented in this paper is aimed at the comparison of the Oscillation-based Built-In Self Test (OBIST) efficiency in covering catastrophic and parametric faults in active analog integrated filters designed in two different technologies. Sallen-Key topologies of low-pass and high-pass filters were used as Circuit Under Test (CUT), designed in 0.35μm and 90nm CMOS technologies. The presented oscillation test strategy uses the on-chip Schmitt oscillator as the reference frequency source to compensate the influence of process parameter variations. Achieved results show that the proposed BIST approach is fully implementable in nanoscale technologies. Finally, dependence of the fault coverage on the oscillation frequency value was investigated.

An approach towards selection of the oscillation frequency for oscillation test of analog ICs

The paper deals with a new approach to selection of the optimum value of the oscillation frequency towards increasing the efficiency of the oscillation-based test methods in covering hard-detectable short faults in nanoscale technologies. For this purpose, the Describing-Function analysis was used to calculate of the oscillation frequency of a simple oscillator (an analog circuit under test) modeled in MATLAB. Accuracy of the model was evaluated through comparison of computed parameters to parameters achieved for the same circuit in Cadence.

130 nm CMOS Bulk-Driven Variable Gain Amplifier for Low-Voltage Applications

In this paper, a variable gain amplifier (VGA) designed in 130 nm CMOS technology is presented. The proposed amplifier is based on the bulk-driven (BD) design approach, which brings a possibility t...

Comparison of gate-driven and bulk-driven current mirror topologies

In this paper, different topologies of gate-driven and bulk-driven current mirrors designed in 90 nm CMOS technology are presented. Since the conventional MOS transistors can work as a bulk-driven device, there is no need for any modification of the existing MOSFET structure or technology process. The bulk-driven current mirror is capable of operating at power supplies down to the threshold voltage of a standard MOS device. Bulk-driven current mirror topologies were compared to their gate-driven equivalents in terms of main properties and output characteristics. The achieved results prove that the bulk-driven design technique is very promising towards ultra low-voltage analog ICs.

Low-voltage bulk-driven variable gain amplifier in 130 nm CMOS technology

In this paper, a variable gain amplifier designed in 130 nm CMOS technology is presented. The proposed amplifier is based on the bulk-driven approach, which brings a possibility to operate with low supply voltage (i.e. 0.6 V). Since the supply voltage of only 0.6 V is used for the amplifier to operate, there is no latchup risk that usually represents the main drawback of the bulk-driven approach. As an input stage, bulk driven transistors are used, which makes possible to operate in the rail-to-rail input voltage range. Achieved simulation results indicate that gain of the proposed VGA can be varied in a wide range, which together with the low supply voltage feature make the proposed amplifier useful for low-voltage and low-power applications.

OBIST strategy versus parametric test - Efficiency in covering catastrophic faults in active analog filters

This paper deals with the comparison of the fault coverage of catastrophic faults in active analog integrated filter obtained by the measurement of filter parameters and by the Oscillation-based Built-In Self Test (OBIST) approach. In our experiment, firstly, the cut-off frequency, ripple in the pass band, DC gain in pass band and group delay of the filters have been monitored in the operating mode. Then, during the test mode (OBIST), the filter is transformed to an oscillator, and the oscillation frequency is compared to the frequency from a dedicated on-chip reference oscillator to compensate undesired influence of technology variations. The obtained results on the efficiency of both approaches are compared.