Viera Stopjakova

New OBIST Using On-Chip Compensation of Process Variations Toward Increasing Fault Detectability in Analog ICs

A new on-chip oscillation test strategy for analog and mixed-signal circuits is presented. In the proposed method, onchip Schmitt trigger is used as the on-chip frequency reference to compensate the influence of process parameter variations. Furthermore, this solution also brings the possibility to implement Oscillation-based Built-In Self-Test (OBIST) for analog and mixed-signal integrated circuits. The proposed OBIST strategy has been experimentally applied to active analog integrated filters, and its efficiency in detecting hard-detectable catastrophic faults is presented. To demonstrate applicability of the proposed method also in nanoscale technologies, the method has been used to test a noninverting amplifier designed in 90 nm CMOS technology. Consequently, the impact of scaling was analyzed and the method efficiency in covering catastrophic faults achieved for 0.35 μm and 90 nm CMOS technology were compared.

Increasing the efficiency of analog OBIST using on-chip compensation of technology variations

A new strategy for on-chip test of an operational amplifier as a part of complex analog and mixed-signal systems is described. During test mode, the operational amplifier is disconnected from the rest of the circuit and transformed to an oscillator. To evaluate the circuit, its oscillation frequency is then compared to a frequency given by a Schmitt trigger oscillator, used as the on-chip reference to compensate technology variations. This method might bring a possibility to implement the Oscillation-based Built-In Self-Test (OBIST) for operational amplifiers as a part of complex systems.

Clockless Implementation of LEON2 for Low-Power Applications

Vower consumption has become increasingly more important with the advent mobile and wireless devices. This paper presents a clockless implementation of LEON2 processor IP core as a possible solution to the reduction of the processor power consumption. The de-synchronization methodology can be considered as a fast and efficient way to convert synchronous circuits into asynchronous ones. The design flow that is used for the de-synchronization works with a synthesizable HDL specification of the circuit, using the conventional synchronous HDL constructs. Standard synchronous design tools can be used, however, in a more elaborate way. The de-synchronized LEON2 processor could provide a low power, low EMI, clock-jitter-free and clock-skew-free solution of a full featured opensource 32-bit processor.

Application of I DDT test towards increasing SRAM reliability in nanometer technologies

Dynamic supply current test method (IDDT test) in static random access memory (SRAM) cell arrays is addressed in order to unveil weak open defects. Simulations were carried out on a 64-bit SRAM circuit, where several parameters of the IDDT waveform were monitored. The SRAM circuit was designed in a 90 nm CMOS technology. Efficiency of IDDT test in unveiling open defects was evaluated and the achieved results were compared for four SRAM arrays with cells of different cell ratio (CR). Moreover, a solution for transformation of the dynamic current to voltage is presented. After the transformation of the current waveform to a voltage waveform, the parameters of the voltage waveform similar to those of the current waveform are easily monitored and evaluated.

Numerical method for DC fault analysis simplification and simulation time reduction

This paper presents a numerical approach to DC fault analysis of analog circuits that improves the total computational time and reduces the total complexity of such analysis. The reduction is achieved by utilization of calculus that can substitute conventional simulations and thus, significantly reducing computational time. A detailed description of the approach including its mathematical background is presented. Accuracy and time efficiency are demonstrated on a test circuit.

Digital methods of offset compensation in 90nm CMOS operational amplifiers

This paper deals with comparison of two discrete methods for digital trimming of the input offset voltage in operation amplifiers designed in 90nm CMOS technology. Two different topologies based on the binary weighed ladder, one using successive approximation register (SAR) and the other employing a simple counter, were compared. Furthermore, a correction circuit was proposed and used to form the mean offset voltage and increase the probability that its value after trimming process will be near zero. Finally, achieved results and improvements are discussed.

Efficiency of oscillation-based BIST in 90nm CMOS active analog filters

Research presented in this paper is aimed at the comparison of the Oscillation-based Built-In Self Test (OBIST) efficiency in covering catastrophic and parametric faults in active analog integrated filters designed in two different technologies. Sallen-Key topologies of low-pass and high-pass filters were used as Circuit Under Test (CUT), designed in 0.35μm and 90nm CMOS technologies. The presented oscillation test strategy uses the on-chip Schmitt oscillator as the reference frequency source to compensate the influence of process parameter variations. Achieved results show that the proposed BIST approach is fully implementable in nanoscale technologies. Finally, dependence of the fault coverage on the oscillation frequency value was investigated.

Automated Synchronous-to-Asynchronous Circuits Conversion: A Survey

Automated synchronous-to-asynchronous circuit conversion can be considered as one area of clockless design style, which is becoming more and more interesting for synchronous designers with lack of knowledge and experience in the real asynchronous circuit design. Another reason why it is becoming so interesting is that the languages and design styles for specification of asynchronous circuits require a learning curve to understand, become proficient with them, and to use them effectively. Hence, numerous approaches for automated conversion of synchronous circuits into their asynchronous counterparts have been proposed in recent years. The main reason is the exploitation of the often claimed advantages of asynchronous circuits, especially their lower power consumption. This paper surveys some of the available well-known synchronous-to-asynchronous conversion techniques and tries to present both their positive and negative properties.

Task scheduler for dual-core real-time systems

This paper presents the design of a coprocessor that performs conflict-free task scheduling for dual-core real-time systems. The solution proposed in this paper is based on two algorithms: Earliest Deadline First (EDF) algorithm that is proved to always find an optimal ordering of hard real-time tasks and the priority-based FIFO algorithm that is suitable for non-real-time tasks. The proposed coprocessor can efficiently handle any combination of both types of tasks even though they use different parameters for scheduling. Thanks to HW implementation of the scheduler, the operations are performed in one clock cycle regardless of the current and the maximum number of tasks in the system. The proposed coprocessor is optimized for dual-core CPUs, which can lead to higher performance of real-time embedded systems. Two different approaches for dual-core systems are proposed: semaphore approach and simultaneous processing approach. The simultaneous approach allows the coprocessor to accept and perform both instructions of both CPU cores simultaneously without any conflicts. Both approaches were verified using simplified version of UVM and applying 16 million instructions with randomly generated deadline values. Achieved synthesis results are discussed.

Improved Task Scheduler for Dual-Core Real-Time Systems

This paper presents the design of an improved coprocessor that performs conflict-free task scheduling for dual-core real-time systems. The solution proposed in this paper is based on two algorithms: Earliest Deadline First (EDF) algorithm that is proved to always find an optimal ordering of hard real-time tasks and the priority-based FCFS algorithm that is suitable for non-real-time tasks. The proposed coprocessor can efficiently handle any combination of both types of tasks even though they use different parameters for scheduling. Thanks to HW implementation of the scheduler, the operations are performed in one clock cycle regardless of the current and the maximum number of tasks in the system. The proposed coprocessor is optimized for dual-core CPUs, which can lead to higher performance of real-time embedded systems. Two different approaches for dual-core systems are proposed: semaphore approach and simultaneous processing approach. The simultaneous approach allows the coprocessor to accept and perform both instructions of both CPU cores simultaneously without any conflicts. Both approaches were verified using simplified version of UVM and applying 128 million instructions with randomly generated deadline values. Chip area costs are reduced by up to 35% by performing time precision optimization. The total power consumption is theoretically reduced by up to 50% during the time when the coprocessor is not used by any CPU because the dynamic power consumption is reduced dramatically.