Ludovic Devaux

Flexible interconnection network for dynamically and partially reconfigurable architectures

The dynamic and partial reconfiguration of FPGAs enables the dynamic placement in reconfigurable zones of the tasks that describe an application. However, the dynamic management of the tasks impacts the communications since tasks are not present in the FPGA during all computation time. So, the task manager should ensure the allocation of each new task and their interconnection which is performed by a flexible interconnection network. In this article, various communication architectures, in particular interconnection networks, are studied. Each architecture is evaluated with respect to its suitability for the paradigm of the dynamic and partial reconfiguration in FPGA implementations. This study leads us to propose the DRAFT network that supports the communication constraints into the context of dynamic reconfiguration. We also present DRAGOON, the automatic generator of networks, which allows to implement and to simulate the DRAFT topology. Finally, DRAFT and the two most popular Networks-on-Chip are implemented in several configurations using DRAGOON, and compared considering real implementation results.

Flexible communication support for dynamically reconfigurable FPGAS

Dynamic reconfiguration of FPGAs allows the dynamic management of various tasks that describe an application. This new feature permits, for optimization purpose, to place tasks on line in an available region of the FPGA. Dynamic reconfiguration of tasks leads to some communication problems since tasks are not present in the matrix during all computation time. This dynamicity needs to be supported by the interconnection network. In this paper, we propose the implementation of a flexible interconnection network supporting such dynamicity. The proposed architecture is fully compliant with the present state-of-art dynamically reconfigurable circuits such as Xilinx Virtex family of FPGA.

DRAFT: Flexible interconnection network for dynamically reconfigurable architectures

Dynamic and partial reconfiguration allows to place on line the various tasks that describe an application, in available regions of an FPGA. This new featur leads notably to communication problems since tasks are not present in the matrix during all computation time. In this article, we compare popular interconnection architectures. From this study, the DRAFT network is designed to support the communication constraints required by the dynamic reconfiguration. DRAGOON, the automatic generator of networks providing the DRAFT topology, is presented with DRAFT first implementation results and network performances.

R2NoC: Dynamically Reconfigurable Routers for Flexible Networks on Chip

The use of dynamically and partially reconfigurable resources permits to support complex applications. If dynamic and partial reconfiguration offers new possibilities for applicative implementations, it could also provide new ways to design efficient interconnection architectures. In this way, R2NoC, a Network on Chip constituted of dynamically reconfigurable routers is presented. First characterizations of this network are provided through the physical implementation of one single router in a modern FPGA.

Re 2 DA: Reliable and reconfigurable dynamic architecture

Exploiting partial reconfiguration of commercial FPGAs allows the construction of dynamic multi-processor system-on-chip (MPSoC). This solution offers many advantages such as: low development costs and maintains flexibility as well as high computation power. However, FPGAs are susceptible to electronic particles which can toggle configuration bit values and hence change the correct function of the design. Moreover, that could be important in critical applications which require safety and security. Hence using FPGA requires to integrate fault-tolerance schemes into the system. The reliable MPSoC system called Re2DA, presented in this paper, guarantee the system operation by the use of dynamic reconfiguration. Nearly no hardware overhead is required to perform fault-tolerant feature in the system while timing overhead is kept relatively low.

OCEAN, a flexible adaptive Network-On-Chip for dynamic applications

The dynamic and partial reconfiguration of FPGAs enables the dynamic placement of applicatives tasks in reconfigurable zones. However, the dynamic management of the tasks impacts the communications since they are not present in the FPGA during all computation time. So, the task manager should ensure the allocation of each new task and their interconnection which is performed by a flexible interconnection network. In this article, various interconnection networks are studied. Each architecture is evaluated with respect to its suitability for the paradigm of the dynamic and partial reconfiguration in FPGA implementations. This study leads us to propose the OCEAN network that supports the communication constraints into the context of dynamic reconfigurations. Thanks to a generic platform allowing in situ characterizations of network performances, fair comparisons of various Networks-On-Chip can be realized. The FPGA and ASICs implementations of the OCEAN network are also discussed.