Daniel Kehrer

40-Gb/s 2:1 multiplexer and 1:2 demultiplexer in 120-nm standard CMOS

We present an integrated 2:1 multiplexer and a companion 1:2 demultiplexer in CMOS. Both integrated circuits (ICs) operate up to a bit rate of 40 Gb/s. The 2:1 multiplexer features two in-phase data inputs which are achieved by a master-slave flip-flop and a master-slave-master flip-flop. Current-mode logic is used because of the higher speed compared to static CMOS and the robustness against common-mode disturbances. The multiplexer uses no output buffer and directly drives the 50-/spl Omega/ environment. An inductance connected in series to the output in combination with shunt peaking is used to enhance the bandwidth of the multiplexer. Fully symmetric on-chip inductors are used for peaking. The inductors are mutually coupled to save chip area. Lumped equivalent models of both peaking inductors allow optimization of the circuit. The ICs are fabricated in a 120-nm standard CMOS technology and use 1.5-V supply voltage. Measured eye diagrams of both ICs demonstrate their performance.

A high sensitivity static 2:1 frequency divider up to 19 GHz in 120 nm CMOS

A completely integrated 19 GHz static 2:1 frequency divider in 120 nm CMOS is presented. The divider operates up to 19 GHz and features an enhanced input sensitivity of 0 dBm over a broad input band of 15 GHz. The circuit draws 44 mA from a single 1.5 V supply. To drive 50 /spl Omega/ loads up to 9.5 GHz, an output buffer is also included in the divider circuit.

Modeling of monolithic lumped planar transformers up to 20 GHz

A new method for characterization of monolithic lumped planar transformers is proposed in this paper. A lumped low-order equivalent model is derived from the physical layout using a new expression for the substrate loss. Two transformers are considered in detail, showing excellent agreement between simulation and measurement.

A 75 nm 7 Gb/s/pin 1 Gb GDDR5 Graphics Memory Device With Bandwidth Improvement Techniques

Modern graphics subsystems (gaming PCs, midhigh end graphics cards, game consoles) have reached the 2.6-2.8 Gb/s/pin regime with GDDR3/GDDR4, and experimental work has shown per pin rates up to 6 Gb/s/pin on individual test setups. In order to satisfy the continuous demand for even higher data bandwidths and increased memory densities, more advanced design techniques are required. This paper describes a 7 Gb/s/pin 1 Gb GDDR5 DRAM and the circuit design and optimization features employed to achieve these speeds. These features include: an array architecture for fast column access, a command-FIFO designed to take advantage of special training/tracking requirements of the GDDR5 interface, a boosting transmitter to increase read eye height, sampling receivers with pre-amplification and offset control, multiple regulated internal voltage (VINT = 1.3 V) domains to control on chip power noise, and a high-speed internal VINT power generator system. The memory device was fabricated in a conventional 75 nm DRAM process and characterized for a 7 Gb/s/pin data transfer rate at 1.5 V Vext.

A 17 GHz dual-modulus prescaler in 120 nm CMOS

A completely integrated 17 GHz prescaler with programmable ratios of 4 and 5 is presented. The prescaler uses high speed differential current-mode logic and merged AND-gates. Over a band of 15 GHz the prescaler features an enhanced input sensitivity of less than 0 dBm. The circuit draws 47 mA from a single 1.5 V supply. An output buffer is also included in the circuit to drive 50 /spl Omega/ loads. The circuit is manufactured in a 120 nm CMOS technology.

A low power 13-Gb/s 2/sup 7/-1 pseudo random bit sequence generator IC in 120 nm bulk CMOS

We present a pseudo random bit sequence (PRBS) generator with a sequence length of 2/sup 7/-1. The circuit uses a 7 bit full rate shift register with a linear XOR feedback and works up to data rates of 13 Gb/s. The PRBS generator features a divide by 2 trigger divider, two 3 bit shifted outputs and an autostart logic. The circuit draws 137 mA from a single 1.5 V supply. The circuit is manufactured in 120 nm bulk CMOS technology.

40Gb/s 2:1 multiplexer and 1:2 demultiplexer in 120nm CMOS

A 40Gb/s 2:1 multiplexer in 120nm 1.2V CMOS uses inductive peaking and output series inductor. A companion 1:2 demultiplexer is also described.

A 30-gb/s 70-mW one-stage 4:1 multiplexer in 0.13-/spl mu/m CMOS

A completely integrated 4:1 multiplexer for high-speed operation and low power consumption is presented. The circuit uses a new architecture where four data streams are multiplexed in one stage. Pulses with a duty cycle of 25% switch the inputs to the multiplexer (MUX) output. The pulses are generated from the clock signal and the divided clock signal. Measurement results show the performance of the IQ divider. Current-mode logic is used because of the higher speed compared to static CMOS and the robustness against common-mode disturbances. The multiplexer uses no output buffer and directly drives the 50-/spl Omega/ environment. The lower number of gates compared to the conventional tree topology enables low-power design. Relaxed timing conditions are additional benefits of the one-stage MUX topology. The IC is fabricated in a 0.13-/spl mu/m standard bulk CMOS technology and uses 1.5-V supply voltage. The MUX works up to 30 Gb/s and consumes 70 mW.

Cascading Techniques for a High-Speed Memory Interface

A memory interface operating up to 5.3Gb/s in a 70nm standard DRAM process is presented. The interface uses differential point-to-point signaling in a chain of 6 devices, in transparent- or resample-repeat mode. Transparent-repeat mode measurements at 4.8Gb/s show eye reduction of 8% Ul per device due to jitter accumulation. The last device in the repeat chain has an eye opening of 0.5UI at BER < 1012. The transparent-repeat mode consumes 40% less power and has 80% less latency than resample mode

A 24 GHz dual-modulus prescaler in 90 nm CMOS

We present a completely integrated 24 GHz prescaler with programmable division ratios of /4 and /5. The prescaler uses high speed differential current mode logic. AND-gates are merged with flip-flops for low power consumption and minimum gate delay. Broadband static operation up 24 GHz is achieved with on-chip shunt peaking inductors in the flipflops. A broadband output buffer is included in the circuit to drive 50 /spl Omega/ loads. The circuit draws 49 mA from a single 1.2 V supply. With a reduced supply voltage of 0.9 V the maximum operating frequency of the prescaler is 22 GHz and the total power dissipation is 27 mW. The circuit is manufactured in 90 nm bulk CMOS technology.