Marc Tiebout

Low-power low-phase-noise differentially tuned quadrature VCO design in standard CMOS

This paper describes the design and optimization of VCOs with quadrature outputs. Systematic design of fully integrated LC-VCOs with a high inductance tank leads to a cross-coupled double core LC-VCO as the optimal solution in terms of power consumption. Furthermore, a novel fully differential frequency tuning concept is introduced to ease high integration. The concepts are verified with a 0.25-/spl mu/m standard CMOS fully integrated quadrature VCO for zero- or low-IF DCS1800, DECT, or GSM receivers. At 2.5-V power supply voltage and a total power dissipation of 20 mW, the quadrature VCO features a worst-case phase noise of -143 dBc/Hz at 3-MHz frequency offset over the tuning range. The oscillator is tuned from 1.71 to 1.99 GHz through a differential nMOS/pMOS varactor input.

Advanced Microwave Imaging

Due to the enormous advances made in semiconductor technology over the last few years, high integration densities with moderate costs are achievable even in the millimeter-wave (mm-wave) range and beyond, which encourage the development of imaging systems with a high number of channels. The mm-wave range lies between 30 and 300 GHz, with corresponding wavelengths between 10 and 1 mm. While imaging objects with signals of a few millimeters in wavelength, many optically opaque objects appear transparent, making mm-wave imaging attractive for a wide variety of commercial and scientific applications like nondestructive testing (NDT), material characterization, security scanning, and medical screening. The spatial resolution in lateral and range directions as well as the image dynamic range offered by an imaging system are considered the main measures of performance. With the availability of more channels combined with the powerful digital signal processing (DSP) capabilities of modern computers, the performance of mm-wave imaging systems is advancing rapidly.

Analysis and Design of an Integrated Notch Filter for the Rejection of Interference in UWB Systems

A 0.13-mu m CMOS fourth-order notch filter for the rejection of the 5-6 GHz interference in UWB front-ends is reported. The filter is integrated into an analog front-end for Mode #1 UWB. A thorough analysis based on a simplified model of the filter is carried out. An algorithm for the automatic tuning and calibration of the filter is also discussed and demonstrated. Two versions of the circuit are designed and fabricated: the first comprises a low-noise amplifier and the filter, and the second expands it to a complete front-end. In the latter version the filter was also redesigned. The filter provides more than 35 dB of attenuation and has a tuning range of 900 MHz, adding less than 30% power consumption to the LNA. The out-of-band IIP3 (higher than -13.2 dBm with the filter off) takes a 9-dB advantage from the filter and the compression of the gain due to the out-of-band blocker is reduced by at least 6 dB in the complete front-end. The conversion gain of the front-end is 25 dB per channel, its average noise figure is lower than 6.2 dB, and its in-band 1-dB compression point is higher than - 30 dBm at a power consumption of 32 mW.

A 0.6-V 1.6-mW transformer-based 2.5-GHz downconversion mixer with +5.4-dB gain and -2.8-dBm IIP3 in 0.13-/spl mu/m CMOS

On-chip transformers are best suited to lower the supply voltage in RF integrated circuits. A design method to achieve a high current gain with an on-chip transformer operating in resonance is presented. The proposed method will be proven analytically and has been applied to a downconversion mixer. Thereby part of the overall gain of the mixer has been shifted from the RF input stage to the transformer. Thus, the power consumption has been reduced and, in spite of the low supply voltage, moderate linearity has been achieved. Although the transformer has a bandpass behavior, a 3-dB bandwidth of 900 MHz at a center frequency of 2.5 GHz has been achieved. The downconversion mixer has been realized in 0.13-mum CMOS. It consumes 1.6 mW from a 0.6-V supply. A gain of +5.4 dB, a third-order intercept point of -2.8 dBm, an input 1-dB compression point of -9.2 dBm, and a single-sideband noise figure of 14.8 dB have been achieved

A WiMedia/MBOA-Compliant CMOS RF Transceiver for UWB

A fully integrated WiMedia/MBOA-compliant RF transceiver for UWB data communication in the 3 to 5GHz band is presented. It is designed in a 0.13mum standard CMOS process with 1.5V single supply voltage. The NF is between 3.6 and 4.1dB over all 3 bands. On the TX side, the P1dB is 5dBm supporting an EVM of -28dB and up to -4dBm output power. A single-PLL LO generation is included

MOS varactors with n- and p-type gates and their influence on an LC-VCO in digital CMOS

The influence of the gate doping type of the MOS varactor on frequency tuning, phase noise, and frequency sensitivity to supply-voltage variations of a fully integrated inductance-capacitance voltage-controlled oscillator (LC-VCO) is presented. Three varactors in multifinger layout with shallow trench isolation (STI) are compared. The polysilicon gate is either entirely n- or p-doped or the fingers have alternating n and p doping. Differences in capacitance and quality factor are shown. Two identical VCOs with the varactors having n gates or np gates are realized. Homogenous doping increases the VCO tuning range to 1.31 GHz (/spl plusmn/20%) in comparison to 1.06 GHz (/spl plusmn/15%) obtained by mixed doping. However, mixed doping has the advantages of more linear VCO frequency tuning, lower close-in phase noise, and reduced maximum sensitivity to variations in supply voltage. Several varactor parameters are introduced. They allow prediction of the influence of varactors on the performance of a given VCO. With a current consumption of only 1 mA from a supply voltage of 1.5 V, both VCOs show a phase noise of -115 dBc/Hz at 1-MHz offset from a 4-GHz carrier and a VCO figure of merit of -185.3 dBc/Hz.

A 0.06 mm

GSM-compliant local oscillator consuming a tiny die area of only 0.06 mm and drawing 9 mA from a 1.2 V supply has been designed in a 65 nm CMOS process using thin-oxide devices only. The system is made of a 13 to 15 GHz LC VCO followed by a divide-by-four injection-locked frequency divider. The divider employs a ring oscillator-based topology leading to a two octave locking range with limited area and power consumption. The phase noise at the output of the divider is below -133 dBc/Hz at 3 MHz offset over the tuning range.

^{2}

Sub-harmonic injection locking is employed to generate the fast-hopping carriers required in UWB systems for WiMedia . A very small area 90-nm CMOS prototype synthesizes the frequencies of band group #6 with a hop time shorter than 4 ns . It occupies 0.074 mm2 and draws 30 mA from a 1.2 V supply. Phase noise at 8.71 GHz is -112 dBc/Hz at 1 MHz offset. The design is supported by a thorough analysis that emphasizes the tradeoffs in the parameters of the proposed system.

11 mW Local Oscillator for the GSM Standard in 65 nm CMOS

The present work is focussed on the trade off between conventional RF ESD protection concepts optimized in terms of capacitive load and the frequently discussed RF ESD codesign idea with ESD protection skilfully integrated into RF circuit design. A narrow and a broadband RF test circuit were developed to put the benchmark on a firm basis. RF and ESD experiments are discussed, showing where the higher effort for the codesign approach starts to pay off.

UWB Fast-Hopping Frequency Generation Based on Sub-Harmonic Injection Locking

A fully differential low-voltage mixer topology is presented. The problem of stacking input-, cascode- and switching-transistors within 1.2 V supply voltage is solved by the use of a bulk driven mixer core. In order to demonstrate the feasibility a test chip was manufactured in INFINEON triple well 90 nm standard CMOS process. The differential mixer includes an on-chip resistive 50 /spl Omega/ termination and an operational amplifier for measurements. The chip features a gain of 3.2 dB, a DSB noise figure of 17.4 dB, an input IP3 of -2.1 dBm, an input 1dB compression point of -13.3 dBm and consumes 1.8 mW at a power supply voltage of 1.2 V. The mixer has a 3 dB low-pass bandwidth of 20 GHz.