Martin Wurzer

40-Gb/s 2:1 multiplexer and 1:2 demultiplexer in 120-nm standard CMOS

We present an integrated 2:1 multiplexer and a companion 1:2 demultiplexer in CMOS. Both integrated circuits (ICs) operate up to a bit rate of 40 Gb/s. The 2:1 multiplexer features two in-phase data inputs which are achieved by a master-slave flip-flop and a master-slave-master flip-flop. Current-mode logic is used because of the higher speed compared to static CMOS and the robustness against common-mode disturbances. The multiplexer uses no output buffer and directly drives the 50-/spl Omega/ environment. An inductance connected in series to the output in combination with shunt peaking is used to enhance the bandwidth of the multiplexer. Fully symmetric on-chip inductors are used for peaking. The inductors are mutually coupled to save chip area. Lumped equivalent models of both peaking inductors allow optimization of the circuit. The ICs are fabricated in a 120-nm standard CMOS technology and use 1.5-V supply voltage. Measured eye diagrams of both ICs demonstrate their performance.

42 GHz static frequency divider in a Si/SiGe bipolar technology

Frequency dividers are key components for multi-gigabit-per-second optical fiber links. For this application, maximum speed is mandatory, while the power consumption is not a limiting factor. To date, the highest operating speed for static frequency dividers has been achieved with III-V devices. For AlInAs/GaInAs HBTs with 130 GHz f/sub T/, 39.5 GHz operation is measured, and for 0.1 /spl mu/m InAlAs/InGaAs HEMTs with f/sub T/ of approximately 200 GHz an operating speed of 40.4 GHz is recently reported. The fastest published static silicon divider operates up to 35 GHz. Silicon bipolar technologies offer high reliability and cost-effectiveness. This divider is fabricated in a 0.5 /spl mu/m double-polysilicon self-aligned Si/SiGe heterojunction bipolar technology.

86 GHz static and 110 GHz dynamic frequency dividers in SiGe bipolar technology

We present static and dynamic frequency dividers manufactured in a 200 GHz f/sub T/ SiGe bipolar technology. The static divider has a divide ratio of 32 and operates up to 86.2 GHz. The dynamic divider is based on regenerative frequency division and has a divide ratio of two. It operates up to 110 GHz (limited by the measurement equipment). The power consumption of the static and dynamic frequency dividers is 900 mW and 310 mW, respectively.

A 28-GHz monolithic integrated quadrature oscillator in SiGe bipolar technology

This paper presents a 28-GHz monolithic quadrature voltage-controlled oscillator (QVCO) realized in a preproduction 0.4-/spl mu/m SiGe bipolar technology with 85-GHz transit frequency. QVCOs efficiently drive quadrature modulators and demodulators in receivers or transmitters. At 28.9 GHz, the circuit provides -14.7 dBm of output power and phase noise of -84.2 dBc/Hz at a 1-MHz offset. The two output signals are in quadrature with phase error of about 5/spl deg/. Tuning of the QVCO may be done in the frequency range from 24.8 to 28.9 GHz with nearly constant output power. The circuit consumes 25.8 mA from the 5 V voltage supply.

A 40-Gb/s integrated clock and data recovery circuit in a 50-GHz f/sub T/ silicon bipolar technology

Clock and data recovery (CDR) circuits are key electronic components in future optical broadband communication systems. In this paper, we present a 40-Gb/s integrated CDR circuit applying a phase-locked loop technique. The IC has been fabricated in a 50-GHz f/sub T/ self-aligned double-polysilicon bipolar technology using only production-like process steps. The achieved data rate is a record value for silicon and comparable with the best results for this type of circuit realized in SiGe and III-V technologies.

A 50 GHz implanted base silicon bipolar technology with 35 GHz static frequency divider

A 0.5 /spl mu/m silicon bipolar technology for mixed digital/analogue RF applications is presented. Very steep base profiles are realized by ion implantation and subsequent base diffusion. Cut-off frequencies and maximum oscillation frequencies of 50 GHz and ECL gate delay of 16 ps are obtained without increasing the process complexity in comparison to a 0.8 /spl mu/m production technology. A static 2:1 frequency divider operates up to 35 GHz, the highest value reported for any silicon based technology.

36 GHz dual-modulus prescaler in SiGe bipolar technology

Presents a dual-modulus prescaler with divide ratios of 256 and 257. The circuit uses static divider stages and differential current-mode logic. AND-gates are merged with flip-flops to achieve high operating frequencies at low power consumption. The prescaler operates with input frequencies ranging from below 1 GHz up to 36.4 GHz. It consumes 34.2 mA from a 3 V supply. The circuit is manufactured in a 0.4 /spl mu/m SiGe bipolar technology.

71.8 GHz static frequency divider in a SiGe bipolar technology

A 2:1 static frequency divider fabricated in a 0.35 /spl mu/m SiGe bipolar technology is described. It operates up to 71.8 GHz and draws 132 mA from a single 4.5 V supply. Continuous operation up to the maximum operating frequency of 71.8 GHz has been demonstrated. This operating frequency is the highest achieved for this type of circuit in Si-based technologies and comparable with the fastest static dividers realized in III-V technologies.

40 Gbit/s 2/sup 7/-1 PRBS generator IC in SiGe bipolar technology

A pseudo-random bit sequence (PRBS) generator with a sequence length of 2/sup 7/-1 is presented. The circuit is based on a linear feedback shift register operating at half the output data rate. It is manufactured in a pre-production SiGe bipolar technology with a cut-off frequency f/sub T/ of 106 GHz. The PRBS generator operates up to a maximum data rate of 40 Gbit/s and consumes 265 mA from a -4.5 V supply.

2-GHz/2-mW and 12-GHz/30-mW dual-modulus prescalers in silicon bipolar technology

Two dual-modulus prescalers manufactured in a low-cost silicon bipolar technology are presented. The first circuit is optimized for low power consumption and operates up to 2 GHz at a power consumption of 2 mW. The second prescaler is optimized for high speed and operates up to 12 GHz with a power consumption of 30 mW. The prescalers have selectable divide ratios of 128/129 and 256/257, respectively.