Hans-Dieter Wohlmuth

A monolithic transformer coupled 5-W silicon power amplifier with 59% PAE at 0.9 GHz

This paper presents the circuit design and application of a monolithically integrated silicon radio-frequency power amplifier for 0.8-1 GHz. The chip is fabricated in a 25-GHz-f/sub T/ silicon bipolar production technology (Siemens B6HF). A maximum output power of 5 W and maximum efficiency of 59% is achieved. The chip is operating from 2.5 to 4.5 V. The linear gain is 36 dB. The balanced two-stage circuit design is based fundamentally on three on-chip transformers. The driver stage and the output stage are connected in common-emitter configuration. The input signal can be applied balanced or single-ended if one input terminal is grounded. One transformer at the input acts as balun as well as input matching network. Two transformers acts as interstage matching network.

Lumped and distributed lattice-type LC-baluns

This paper presents two balun circuits derived from the lumped Lattice-type LC-balun. First the lumped LC-balun bridge elements are substituted by microstrip lines. This results in an improved performance at the 2nd and 3rd harmonic frequency for RF power amplifier output baluns. Secondly, the lumped Lattice-type LC-balun is extended to a dual band balun. Independent impedance transformation and balun conversion can be done at two different frequencies. The design equations are derived.

40-Gb/s 2:1 multiplexer and 1:2 demultiplexer in 120-nm standard CMOS

We present an integrated 2:1 multiplexer and a companion 1:2 demultiplexer in CMOS. Both integrated circuits (ICs) operate up to a bit rate of 40 Gb/s. The 2:1 multiplexer features two in-phase data inputs which are achieved by a master-slave flip-flop and a master-slave-master flip-flop. Current-mode logic is used because of the higher speed compared to static CMOS and the robustness against common-mode disturbances. The multiplexer uses no output buffer and directly drives the 50-/spl Omega/ environment. An inductance connected in series to the output in combination with shunt peaking is used to enhance the bandwidth of the multiplexer. Fully symmetric on-chip inductors are used for peaking. The inductors are mutually coupled to save chip area. Lumped equivalent models of both peaking inductors allow optimization of the circuit. The ICs are fabricated in a 120-nm standard CMOS technology and use 1.5-V supply voltage. Measured eye diagrams of both ICs demonstrate their performance.

A high sensitivity static 2:1 frequency divider up to 19 GHz in 120 nm CMOS

A completely integrated 19 GHz static 2:1 frequency divider in 120 nm CMOS is presented. The divider operates up to 19 GHz and features an enhanced input sensitivity of 0 dBm over a broad input band of 15 GHz. The circuit draws 44 mA from a single 1.5 V supply. To drive 50 /spl Omega/ loads up to 9.5 GHz, an output buffer is also included in the divider circuit.

Modeling of monolithic lumped planar transformers up to 20 GHz

A new method for characterization of monolithic lumped planar transformers is proposed in this paper. A lumped low-order equivalent model is derived from the physical layout using a new expression for the substrate loss. Two transformers are considered in detail, showing excellent agreement between simulation and measurement.

A monolithic 2.5 V, 1 W silicon bipolar power amplifier with 55% PAE at 1.9 GHz

A monolithic RF power amplifier for 1.8-2 GHz has been realized in a 50 GHz-f/sub T/ Si bipolar technology and is operating down to supply voltages as low as 1.2 V. The balanced 2-stage power amplifier uses two on-chip transformers as input-balun and for interstage matching, with a high coupling coefficient of k=0.84. At 1.2 V, 2.5 V, and 3 V supply voltage an output power of 0.22 W, 1 W and 1.4 W is achieved, at a power added efficiency of 47%, 55% and 55%, respectively at 1.9 GHz. The small-signal gain is 28 dB.

A low-noise amplifier at 77 GHz in SiGe:C bipolar technology

A single ended low noise amplifler at 77GHz has been designed, implemented, and characterized. The focus was on a low noise flgure, reasonable input and out- put matching, and a high input compression point which are basic requirements for automotive radar applications or car{to{car communication systems. The LNA was fa- bricated in a 225GHz fT SiGe:C bipolar technology. At 77GHz, the measured gain of the LNA is 8.9dB, and the measured noise flgure at 77GHz is 4.8dB. The measured input compression point at 77GHz is -3dBm. The cir- cuit was designed for a supply voltage of 5.5V and draws 22mA.

Low Power Wideband Receiver and Transmitter Chipset for mm-Wave Imaging in SiGe Bipolar Technology

This paper presents a chipset aiming at high resolution imaging systems for real-time people screening applications operating near the W-band. The frequency of operation ranges from 70 GHz to 82 GHz for optimal image resolution and depth of focus. The frequency generation for both receiver and transmitter chips consists of a mixer based frequency quadrupler with an input amplifier requiring -20 dBm of input power. The receiver RFIC contains 4 channels including LO generation and distribution. The measured receiver conversion gain is 23 dB with a SSB NF around 10 dB over a wide frequency range from 70 GHz up to 82 GHz. The transmitter RFIC includes LO generation, distribution and 4 output amplifiers with an output power of more than 0 dBm in a frequency range from 70 GHz to 82 GHz. Both ICs are supplied from a single 3.3 V supply voltage and the power consumption is 180 mW/channel for the receiver and 145 mW/channel for the transmitter.

A fully integrated 4.8-6 GHz power amplifier with on-chip output balun in 38 GHz-f/sub T/ Si-bipolar

A fully integrated radio frequency power amplifier for 4.8-6 GHz has been realized in a 38 GHz-f/sub T/, 0.25 /spl mu/m-Si-BiCMOS technology. The balanced 2-stage push-pull power amplifier uses two on-chip transformers as input balun and for interstage matching and an LC-type output balun with planar inductors. With this output network no external elements are required. At 1.2 V, 1.5 V, 2 V supply voltages output powers of 17 dBm, 18.9 dBm, 20.7 dBm are achieved at 5.8 GHz. The small-signal gain is 23 dB.

25 GHz static frequency divider and 25 Gb/s multiplexer in 0.12 /spl mu/m CMOS

A static 2:1 frequency divider operating up to 25.4 GHz at 41 mA and a 25 Gb/s 2:1 multiplexer at 29 mA implemented in current-mode logic have differential 50 /spl Omega/ inputs and outputs. They are fabricated in a 0.12 /spl mu/m CMOS process and operate from a 1.5 V supply.