Daniel L. Ostapko

MINI: a heuristic approach for logic minimization

MINI is a heuristic logic minimization technique for many-variable problems. It accepts as input a Boolean logic specification expressed as an input-output table, thus avoiding a long list of minterms. It seeks a minimal implicant solution, without generating all prime implicants, which can be converted to prime implicants if desired. New and effective subprocesses, such as expanding, reshaping, and removing redundancy from cubes, are iterated until there is no further reduction in the solution. The process is general in that it can minimize both conventional logic and logic functions of multi-valued variables.

Optimum test patterns for parity networks

The logic related to the error detecting and/or correcting circuitry of digital computers often contains portions which calculate the parity of a collection of bits. A tree structure composed of Exclusive-OR gates is used to perform this calculation. Similar to any other circuitry, the operation of this parity tree is subject to malfunctions. A procedure for testing malfunctions in a parity tree is presented in this report.

Codes for self-clocking, AC-coupled transmission: aspects of synthesis and analysis

We consider NRZI waveform codes thats atisfy a given set of run-length constraints and the upper bound on the accumulated dc charge of the waveform. These constraints enable the codeword to be self-clocking, ac-coupled, and suitable for data processing tape and communication applications. Various aspects of synthesis and analysis of such codes, called (d, k, C) codes, are illustrated by means of several examples. The choice of the initial state of the encoder is shown to influence the length of the data sequence over which the encoder must look-ahead.

On the signal bounding problem in timing analysis

In this paper, we study the propagation of slew dependent bounding signals and the corresponding slew problem in static timing analysis. The selection of slew from the latest arriving signal, a commonly used strategy, may violate the rule of monotonic delay. Several methods for generating bounding signals to overcome this difficulty are described. The accuracy and monotonicity of each method is analyzed. These methods can be easily implemented in a static timer to improve the accuracy.

Generating test examples for heuristic Boolean minimization

This article describes simple methods of generating many-variable test-case problems for heuristic logic minimization studies. Covering problems and coloring problems are converted into Boolean functions that are useful test cases for minimization.

A mapping and memory chip hardware which provides symmetric reading/writing of horizontal and vertical lines

This paper describes a mapping and memory chip hardware for enhancing the performance of an APA display. The approach describes a modification to the primary port of a quasi-two-ported memory. This modification allows several contiguous horizontal or vertical bits to be read or written in one cycle. The number of bits that can be stored is given by the number of memory chips. The hardware modifications can be on or off chip, and if on chip, the chip can still be used as a conventional memory chip. Simple modifications to the hardware will support different screen sizes.

Interactive Design Language: A Unified Approach to Hardware Simulation, Synthesis and Documentation

IDL is a hardware design language in use in the VLSI environment. It incorporates a significant number of high-level features such as groups, subroutines, and labels and is particularly well adapted to dealing with parallelism at the hardware level. In addition to being human intelligible (and therefore appropriate as a documentation medium), IDL code can be used to generate 2-level logic which, under the IDL system, can be manipulated in a number of ways, including product term factoring and minimization, feedback minimization, partitioning, merging, and verification. The IDL system contains several simulators that are driven by IDL code. The most common embodiment of IDL output in hardware is a PLA.

On Complementation of Boolean Functions

A theorem is presented that simplifies the computations necessary for complementing a Boolean function.

On deriving a relation between circuits and input/output by analyzing an equivalent program

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VLSI Circuit Analysis, Timing Verification and Optimization

In this paper, we give an overview of the state-of-the-art in Circuit Analysis, Timing Verification, and Optimization. Emphasis is given to circuit analysis, timing verification and optimization since simulation is covered by C. Terman in this book. Also, the optimization of large circuits is receiving new attention due to the need for timing performance improvement in silicon compilation.