Daniel Lawrence Stasiak

The design and implementation of a first-generation CELL processor

A CELL processor is a multi-core chip consisting of a 64b power architecture processor, multiple streaming processors, a flexible IO interface, and a memory interface controller. This SoC is implemented in 90nm SOI technology. The chip is designed with a high degree of modularity and reuse to maximize the custom circuit content and achieve a high-frequency clock-rate.

Cell processor low-power design methodology

Power consumption is a major challenge in VLSI design. Power-constrained designs must attack power reduction with many techniques and require tools to accurately predict the power consumption. These tools give designers feedback on the efficiency of the power management logic. We present the basic methodology behind cycle-accurate power estimation. This forms a basis for explaining the techniques used to reduce power in the first-generation Cell processor, along with data that correlates our hardware measurements against power estimates.

A cycle accurate power estimation tool

Power consumption is one of the major challenges in VLSI Design. Power constrained designs need tools to accurately predict the power consumption and provide feedback to designers on the efficiency of the power management logic. In this paper we present the methodology behind a cycle accurate power estimation tool. This tool was used to estimate the power of a first generation CELL Processor. The tool extracts switching and clock activity from RTL simulations and applies them to transistor level macro power models to calculate the power for every cycle of the simulation trace

A 2nd generation 440 ps SOI 64 b adder

Silicon-on-insulator (SOI) technology allows higher performance than bulk technology. However, the floating body effect in SOI devices poses challenges via history effects, bipolar currents, and lower noise margins on dynamic circuits. This 64 b adder is used to compute the effective address in a PowerPC/sup TM/ processor. Particular emphasis is on design issues, advantages resulting from unique SOI device structures, and the techniques for controlling floating body effect in partially-depleted devices. Adder performance comparison is shown for bulk CMOS, first-generation SOI CMOS, and second generation SOI CMOS.