Daniel M. Kinzer

New trench MOSFET technology for DC-DC converter applications

ew trench MOSFET technology presented in this paper includes several major technological breakthroughs that significantly improved device performance in DC-DC converter applications. The figure of merit R*AA has reached as low as 12 mOhm.mm/sup 2/ for a 30 VN SyncFET and R*Qg is only 75 is only 75 mOhm.nC for a 30VN Control FET, one of the lowest reported.

1200 V high-side lateral MOSFET in junction-isolated power IC technology using two field-reduction layers

A lateral n-channel MOSFET structure in junction-isolated power IC technology using a P-type field-reduction region over an N-type field-reduction region for high-side and low-side switching applications is described. The concept of using two field-reduction layers has been verified by two-dimensional device simulations and by fabricating devices with breakdown voltage in excess of 1200 V.<<ETX>>

High-density ultra-low R/sub dson/ 30 volt N-channel trench FETs for DC/DC converter applications

This paper presents a new high-density trench MOSFET design with ultra-low R/sub dson/ for DC/DC converter applications. A benchmark low specific on-resistance of 26 m/spl Omega/.mm/sup 2/ at 4.5 V gate bias is reported. A remote contact feature is utilized to obtain such high channel density and corresponding channel conductance. In-circuit efficiency as high as 89% is obtained, which is the best obtained in the industry to date.

High density, sub 10 m Ohm R/sub dson/ 100 volt N-channel FETs for automotive applications

Presented in this paper are the results of high-density trench designs in producing extremely low R/sub dson/ MOSFETs in the 100 VN voltage class. R.A. products of 110 m/spl Omega/.mm/sup 2/ and 125 m/spl Omega/.mm/sup 2/ (depending on design) at 10 V gate are the lowest reported in the industry. The incentive behind this work is to address the rising need of this class of MOSFETs in Automotive applications.

A high density self-aligned 4-mask planar VDMOS process

The fifth generation HEXFET technology achieves its industry leading performance by using innovative self-alignment processes to improve manufacturing precision while cutting the number of process steps. It is a scaled down form of the dominant planar DMOS technology and requires only four masks to build. The self-alignment allows junction depths and feature sizes 30-40% smaller than previous generations. This is especially critical for power FETs with voltage ratings of 100 V or below, since so much of the on-resistance is determined by the width, length, and carrier mobility of the MOS channel. The shallow base greatly reduces JFET resistance while the heavy doping reduces base resistance to enhance ruggedness.