Naresh Thapar

New trench MOSFET technology for DC-DC converter applications

ew trench MOSFET technology presented in this paper includes several major technological breakthroughs that significantly improved device performance in DC-DC converter applications. The figure of merit R*AA has reached as low as 12 mOhm.mm/sup 2/ for a 30 VN SyncFET and R*Qg is only 75 is only 75 mOhm.nC for a 30VN Control FET, one of the lowest reported.

An experimental evaluation of the on-state performance of trench IGBT designs

Abstract The on-state performance of non-self aligned and self aligned trench IGBT designs is experimentally evaluated and compared for the first time in this paper. In contrast to previous reports based only on numerical simulations, experimental results presented in this paper demonstrate that the non-self aligned trench IGBT designs are superior to the self-aligned trench IGBT designs. Furthermore, the variation in the on-state voltage drop with the unit cell parameters of the non-self trench IGBT obtained through numerical simulations show trends that are opposite to those observed experimentally. Our analysis indicates that the disagreement between the experimental and numerical simulation results arises due to the assumption of an ideal ohmic contact to the N + emitter of the TIGBT designs made in previous numerical simulations.

Correlation between the static and dynamic characteristics of the 4.5 kV self-aligned trench IGBT

In this paper, a new procedure to obtain the Reverse Biased Safe Operating Area (RBSOA) of a 4.5 kV self-aligned trench IGBT is presented. Using this procedure, the high voltage RBSOA boundary of a trench IGBT is directly obtained from its static blocking characteristics extended to very high current densities, thereby saving a large amount of computation time and effort required in obtaining the RBSOA through extensive dynamic simulations. In addition, observation of humps in the collector current waveforms during inductive load turn-off are also reported and analyzed.

Influence of the trench corner design on edge termination of UMOS power devices

Abstract In this article, the voltage blocking capability of UMOS power devices is experimentally demonstrated to be limited by the onset of a premature breakdown at the corners of the trench located at the device periphery. With the aid of numerical simulations performed in cylindrical co-ordinates, it is shown for the first time that a race-track shape of the trench gate fingers alleviates the electric fields at the trench corners and maximizes the UMOS voltage blocking capability. In addition, it is also shown that the breakdown voltage at the trench corners can be made to exceed the UMOS unit cell breakdown voltage by using a deep p diffusion around the trenches located at the device periphery.

The accumulation channel driven bipolar transistor (ACBT)

A new three-terminal power switch called the Accumulation Channel driven Bipolar Transistor (ACBT) is proposed and experimentally demonstrated. In the on-state, the characteristics of the ACBT have been found to approach those of a P-I-N rectifier with a MOSFET in series for regulating its current, an equivalent circuit considered to be an ideal for MOS/Bipolar power devices. Unlike previous devices, the high off-state voltage is supported by the formation of a potential barrier to the flow of electrons from the N/sup +/ emitter into the N-drift region within a depletion region. The absence of the P-base region within the ACBT cells eliminates the parasitic four layer PNPN thyristor which had limited the performance of previous MOS/Bipolar transistor structures. Consequently, the ACBT structure has large maximum controllable and surge current densities in addition to low on-state voltage drop and high-voltage current saturation capability.

A comparison of high frequency cell designs for high voltage DMOSFETs

To reduce the conduction and switching losses in a MOSFET, it is desirable to reduce its specific on-resistance (R/sub on,sp/) and the specific input capacitance (C/sub in,sp/). In this paper, the Atomic Lattice Layout (ALL) and the Circular Layout (CL) are compared for a high frequency 400 V n-channel MOSFET with the goal of obtaining the lowest R/sub on/C/sub in/ product. The terrace gate design on ALL, with 6000 /spl Aring/ field oxide under the terrace gate region resulted in a R/sub on/C/sub in/ product of 603 /spl Omega/-pf which is nearly 4 times lower than the conventional DMOS design. It was also found to be superior to the same gate design on a CL. In the cell structure with a floating P/sup +/ diffusion, the gate-drain component (C/sub gd/) of the input capacitance (C/sub in/) was reduced by moving the floating P/sup +/ diffusion edge closer to the P-base edge at the expense of increasing the on-resistance. By studying the variation of the R/sub on/C/sub in/ product as a function of the position of the floating P/sup +/ edge, lowest R/sub on/C/sub in/ products of 452 /spl Omega/-pf and 360 /spl Omega/-pf were obtained for the ALL and CL, respectively. Although the R/sub on/C/sub in/ product of this structure is smaller than the terraced gate structures, the specific on-resistance is larger (98 m/spl Omega/-cm/sup 2/ vs 68 m/spl Omega/-cm/sup 2/ for the ALL and 137 m/spl Omega/-cm/sup 2/ vs 86 m/spl Omega/-cm/sup 2/ for the CL), which implies an increase in the die area. It was shown through simulations that the specific on-resistance did not increase appreciably with a reduction in the gate bias from 10 V to 5 V. Hence operation at 5 V gate bias is recommended to reduce the gate switching losses, which increase as the square of the gate drive voltage.

Analytical model for the threshold voltage of Accumulation Channel MOS-Gate devices

Abstract An analytical model for the threshold voltage of Accumulation Channel MOS-Gate devices is developed for the first time in this paper. Using the model, an equation for the threshold voltage is derived in terms of the design and fabrication process parameters. The values of the threshold voltage predicted by the analytical equation are found to be in excellent agreement with those extracted from numerical simulations and experimental measurements on both silicon and silicon carbide devices. The analysis in this paper is therefore useful in choosing the design and fabrication process parameters required to tailor the threshold voltage of Accumulation Channel MOS-Gate bipolar and unipolar devices.

The accumulation channel driven bipolar transistor (ACBT): a new MOS-gated semiconductor power device

A new power device called the Accumulation Channel driven Bipolar Transistor (ACBT) which has no parasitic thyristor is described in this paper. Unlike previous MOS-gate devices without a P-base region, the potential barrier to the flow of electrons from N/sup +/ emitter into N-drift region in the ACBT is created using the built-in potential of a P-N junction formed along the sidewall and bottom of a shallow trench. The potential barrier height is sufficiently large even at high collector voltages to prevent the direct injection of electrons from N/sup +/ emitter into the N-drift region. An accumulation layer formed along the deep trench sidewall (when the n-channel MOSFET in the ACBT is turned-on) is the only path for electrons to enter into the N-drift region. This results in high voltage current saturation with wide FBSOA for the ACBT. The ACBT has been successfully fabricated using a unique, self-aligned double trench process.

MOS bipolar gate IGBT operation

A new IGBT with a P/sup +/ diverter which is connected to the gate through a series resistance, is proposed in this paper. It was observed from simulations that providing a small current through the diverter resulted in a significant decrease in the device on-state voltage drop. Measurements on fabricated 4 kV IGBTs showed a forward voltage drop of 2.78 V (at collector current density of 100 A/cm/sup 2/) for diverter current of 10 mA (7.38 A/cm/sup 2/), as compared to 3.09 V of the conventional IGBT (without a diverter). After electron irradiation, the devices had a forward voltage drop of 5.02 V (at collector current density of 50 A/cm/sup 2/) for the same diverter current, as compared to 6.48 V for the conventional IGBTs. Furthermore, both the devices had nearly identical turn off time, and excellent latch-up current density.

Influence of the collector resistance on the performance of accumulation channel driven bipolar transistor

Abstract In this paper, the physical mechanism limiting the maximum controllable current density (Jmcc) and safe operating area (SOA) of the accumulation channel driven bipolar transistor (ACBT) is identified and analyzed for the first time. According to our analysis, the hole current flowing into the P+ collector at the shallow trench creates a bias opposing the built-in potential of the P+ collector/N-drift junction due to a finite resistance associated with the contact to the diffused P+ collector region. This lowers the potential barrier established in the narrow mesa region (in between the self-aligned trenches) by the built-in potential of the P+ collector/N-drift junction and the control gate potential and promotes electron injection from the N+ emitter into the N-drift region over the potential barrier. At the onset of electron injection over the potential barrier, gate control over the base drive of the vertical wide base PNP transistor in the ACBT is lost. This hypothesis has been verified through numerical simulations and confirmed by experimental measurements which indicated an increase of over 300% in Jmcc due to a reduction in the contact resistance to the P+ collector region after a post metallization anneal of the fabricated ACBT designs. Based upon these observations, a new ACBT structure with a Schottky collector junction is proposed. It is demonstrated that the proposed ACBT structure has a higher Jmcc and wider SOA in comparison to the ACBT structure with P+ collector region.