Daniel N. Maynard

Measurement and reduction of critical area using Voronoi diagrams

The semiconductor industry recognizes critical area as the scientific cornerstone metric of a designs fault sensitivity. The ability to accurately and quickly extract critical areas is mandatory when considering design for manufacturability (DFM) motivated changes to a portfolio of chip designs which potentially may translate to random defect yield improvements. IBM has invested in a new technique for computing critical areas based upon Voronoi diagrams. A Voronoi diagram uses the Linfin metric to develop artwork that incorporates nearest neighbor information for every point in a plane; we are able to compute the critical area for electrical shorts, opens, and blockage failure mechanisms. Difficult issues, such as accurately accounting for redundant contacts and vias for a given electrical connection, are also considered. The technique provides a number of advantages over previous techniques, and we compare and contrast the technique with other common industry approaches, such as the Monte Carlo and the shapes expansion techniques. Most noteworthy, the Voronoi-diagram-based approach gives an exact answer, eliminating the integration error found in the other techniques. The technique is also extremely fast; we have seen throughput improvements of more than 60 times compared with our Monte Carlo technique for full chip extraction. The Voronoi-diagram critical area extraction can be extended into a visual form. Previous interactive critical area tools have proven to be difficult to use; because the problem of balancing available spacing - and accounting for common-run and corner interactions - is very difficult, even for an experienced designer. Using Voronoi diagrams, the contribution to critical area can be precisely identified and expressed in the form of error shapes or vectors similar to the output from design rule checkers (DRC). Finally we conclude the paper by briefly discussing some of the other potential applications of Voronoi diagrams relating to DFM

Variability and yield improvement: rules, models, and characterization

Yield and variability are becoming detractors for successful design in sub-90-nm process technologies. We consider the fundamental lithography and process issues that are driving variability and yield and the role of design rules in future processes. We examine the importance of layout-aware modeling and layout regularity, including advantages and cost. Characterization structures for examining the electrical effects of device-level variability are discussed as well as circuit techniques for mitigating variability and yield challenges

An information retrieval system for the analysis of systematic defects in VLSI

This work presents a novel information retrieval (IR) tool, designed to help VLSI defect and yield engineers identify potentially defective layout regions. Given a query defect pattern discovered in a manufacturing process, this tool can be used to return similar layout regions in one or more designs ranked by similarity to the query pattern. Defect engineers can then examine these regions in hardware for presence of defects to analyze the cause of the failure. Detailed design considerations, such as feature extraction and clustered search, as well as some real-world search results, are presented and discussed.

Technology assessment of commercially available critical area extraction tools

In the 1990s, the semiconductor industry witnessed a philosophical change in the subject of modeling wafer final test yields. The calculation of average faults per chip has been historically calculated as the product of chip area and fault density, and often incorrectly referred to as defect density. For more than 20 years, several pioneering researchers, representing both academia and industry, have advocated a more accurate estimation of average faults per chip by using critical area, a better metric of chip sensitivity to defect mechanisms. The implementation of this concept requires sophisticated software tools that interrogate the physical design data. At the request of the member companies, International SEMATECH launched a study in 1999 of four commercially available critical area extraction (CAE) tools, with a primary objective of providing an independent technical assessment of capability, performance, accuracy, ease of use, features, and other distinguishing characteristics. Each of the tools were run on several product designs from Agilent Technologies and IBM Microelectronics. The CAE tools were all installed and evaluated at a common member company location, and each of the tool suppliers were visited, providing detailed visibility into the suppliers environment. This paper will review the evaluation methodology, and summarize the findings and results of this International SEMATECH sponsored study.

Wafer line productivity optimization in a multi-technology multi-part-number fabricator

Successful semiconductor manufacturing is driven by wafer-level productivity. Increasing profits by reducing manufacturing cost is a matter of optimizing the factors contributing to wafer productivity. The major wafer productivity components are chips per wafer (CPW), wafer process or fabricator yield (WPY) and wafer final test (WFT) or functional yield. CPW is the count of product chips fitting within the useable wafer surface, and is dependent upon the chip size, dicing channel (kerf) space, and wafer-field size. WPY yield is the percentage of wafers successfully exiting the line; losses include scrap for broken wafers and failed-wafer specifications. WFT yield is the percent of chips that meet all final parametric functional electrical test specifications. Thus, the total wafer level productivity (GCPW) is described by GCPW=CPW/spl middot/WPY/spl middot/WFT. IBMs Vermont fabricator is one of the few in the industry that manufactures DRAMs, SRAMs, microprocessors, ASICs, custom logic, mixed signal, and foundry products, all on the same production floor. The product portfolio spans 12 base technologies across four photolithographic generations from 0.8 /spl mu/m to 0.225 /spl mu/m, with development of 0.18 /spl mu/m. This also encompasses 40 major process flows and over 4000 active part numbers. Such staggering complexity has motivated IBM to consider all possible optimization of these productivity components. This paper describes some of the techniques that have been deployed to achieve this goal.

Moving Carefully Towards Model-based Layout Optimization and Checking

IBM has taken several steps in developing an analysis and optimization framework for VLSI layouts. We have deployed automated tools to reduce the sensitivity of designs to certain defect mechanisms in the manufacturing process. We see a clear need for expanding and refining tMs work and then integrating it with rigorous characterization of manufacturing processes and at the same time developing and integrating an overall trade-off theory showing the interaction of different layout-based yield-enhancement actions.

High-Value Design Techniques for Mitigating Random Defect Sensitivities

Todays sophisticated design-for-manufacturability (DFM) methodologies provide a designer with an overwhelming amount of choices, many with significant costs and unclear value. The technology challenges of subwavelength lithography, new materials, device types/sizes, etc., can mask the underlying random defect yield contribution which ultimately dominates mature manufacturing, and the distinction between technology limitations and process excursions must also be understood. The best DFM strategy fully exploits all of the available techniques that mitigate a designs sensitivity to random defects where the value is clearly quantifiable, yet few designers seize this opportunity. This paper provides a roadmap through the entire design flow and gives an overview of the various options.