Richard J. Rassel

CMOS Imager with Copper Wiring and Lightpipe

A CMOS imager technology is described, which uses Cu wiring and a polymer lightpipe. The microlens height must be optimized when using the lightpipe, so that light is focused into the top of the lightpipe rather than onto the photodiode. A SiN layer is used on the sidewalls to reflect light that enters the top of the lightpipe down onto the photodiode. The SiN layer also forms a hermetic seal, which protects the Cu wiring from ambient moisture. Using this structure, high quantum efficiency can be achieved for a 2.2 mum pixel and high reliability is demonstrated

Stitched large format CMOS image sensors for dental x-ray digital radiography

In this paper, we present a family of large format CIS’s designed for dental x-ray applications. The CIS areas vary from small 31.5mm x 20.1mm, to medium 34.1mm x 26.3mm, to large 37.1mm x 26.3mm. Pixel size is 19.5um x 19.5um. The sensor family was fabricated in a 0.18um CIS process. Stitching is used in the CIS fabrication for the medium and large size sensors. We present the CIS and detector system design that includes pixel circuitry, readout circuitry, x-ray trigger mechanism, scintillator, and the camera electronics. We also present characterization results including the detector performances under both visible light and x-ray radiation.

A capacitance reliability degradation mechanism in Hyper-abrupt junction varactors

Junction varactors form key passive components for RF and analog application where capacitance could be tuned by a control voltage. This paper details and models a reliability degradation mechanism due to electron trapping at the side of shallow trench isolation (STI) of the varactor, leading to systematic capacitance degradation as function of time and stress conditions. A key dimension which controls this mechanism is the anode width or spacing between STI, where a minimum value should be defined to meet reliability targets.

Stress migration in a copper - Aluminum hybrid technology

Stress migration (SM) time, temperature and process dependencies are investigated using a highly sensitive tungsten to copper interface combined with “plate-nose” and “mesh-nose” structures to accelerate the SM mechanism. Voids formed below the W via on the nose, and the resistance increases caused by these voids peaked at temperatures of 300-325°C. The effects of several copper line and tungsten via process steps are discussed. Process steps which modulated the Cu surface and Cu to via bottom interface had the largest effects.

Interconnect and Packaging Technology for CMOS Image Sensors (Invited)

2. Basis Operation The CMOS imager consists of an array of pixels that detect the incident light. A commonly used pixel is the four transistor or “4T” cell (Fig. 1) [2]. To capture an image, the photodiode is first reversed biased (set to Vdd) using the reset gate and transfer gate (Fig. 2). When the shutter of the camera is opened, light that is incident on the photodiode will generate electron-hole pairs. To sense the charge in the photodiode, the transfer gate is turned on and the charge is moved to the floating diffusion. This changes the potential on the gate of the the source-follower circuit, and the resulting signal is detected at the output of the pixel by turning on the row select transistor. The photo-diode area is much smaller than the total area of the pixel. To overcome this loss of sensitivity, microlenses are used to focus light on the photo-diodes [3]. The quantum efficiency (i.e., the percentage of photogenerated carriers that are detected for each incoming photon) is greatly improved by using microlenses . In order to capture color information from the broad bandwidth incident light, color filters are used so that each pixel captures mainly one color of light (i.e., red, green, or blue). The color filters consist of dyed photoresist that is arranged in alternating rows or either green and blue or green and red [4]..

Bond Pad Optimization for CMOS Imager with Chip Scale Package

Three novel CSP pad designs in a 0.18mum CMOS image sensor Cu interconnect technology were analyzed for use with a wafer level CSP (WLCSP) package. The CSP pad designs used various combinations of available aluminum and tungsten interconnect levels in order to improve the cross-sectional area without increasing the total stack height of the Cu interconnect technology. It was found that by increasing the cross-sectional area of the CSP pads the T-connections formed in the CSP process had improved (tighter) resistance distributions