William C. Leipold

TCAD development for lithography resolution enhancement

Advances in lithography have contributed significantly to the advancement of the integrated circuit technology. While nonoptical next-generation lithography (NGL) solutions are being developed, optical lithography continues to be the workhorse for high-throughput very-large-scale integrated (VLSI) lithography. Extending optical lithography to the resolution levels necessary to support today’s aggressive product road maps increasingly requires the use of resolution-enhancement techniques. This paper presents an overview of several resolution-enhancement techniques being developed and implemented in IBM for its leading-edge CMOS logic and memory products.

Alternating phase-shifted mask for logic gate levels, design, and mask manufacturing

While the benefits of alternating phase shifted masks in improving lithographic process windows at increased resolution are well known throughout the lithography community, broad implementation of this potentially powerful technique has been slow due to the inherent complexity of the layout design and mask manufacturing process. This paper will review a project undertaken at IBMs Semiconductor Research and Development Center and Mask Manufacturing and Development facility to understand the technical and logistical issues associated with the application of alternating phase shifted mask technology to the gate level of a full microprocessor chip. The work presented here depicts an important milestone toward integration of alternating phase shifted masks into the manufacturing process by demonstrating an automated design solution and yielding a functional alternating phase shifted mask. The design conversion of the microprocessor gate level to a conjugate twin shifter alternating phase shift layout was accomplished with IBMs internal design system that automatically scaled the design, added required phase regions, and resolved phase conflicts. The subsequent fabrication of a nearly defect free phase shifted mask, as verified by SEM based die to die inspection, highlights the maturity of the alternating phase shifted mask manufacturing process in IBMs internal mask facility. Well defined and recognized challenges in mask inspection and repair remain and the layout of alternating phase shifted masks present a design and data preparation overhead, but the data presented here demonstrate the feasibility of designing and building manufacturing quality alternating phase shifted masks for the gate level of a microprocessor.

Optimizing style options for subresolution assist features

Sub-resolution assist features (SRAF) have been shown to provide significant process window enhancement and across chip line-width variation reduction when used in conjunction with modified illumination lithography. Work previously presented at this conference has focused on the optimization of sraf design rules that specify the predominantly one dimensional placement and width of assist features as a function of layout pitch. This paper will recount the optimization of SRAF style options that specify how SRAF are to behave in realistic two dimensional circuit layouts. Based on the work done to strike the correct balance between sraf manufacturability, CAD turnaround time, and lithographic benefit in IBMs early product implementation exercises, the evolution of sraf style options is presented. Using simulation as well as exposure data, this paper explores the effect of various two dimensional sraf layout solutions and demonstrates the use of model based verification in the optimization of sraf style options.

ASIC data preparation management for OPC

ASIC layout data, which can be large and typically with little hierarchy, can prove challenging for complex optical proximity correction (OPC) operations. Thoughtful coordination between the ASIC library designers and the OPC code developers in terms of design and execution methodologies can result in large savings in run time and additional hierarchy flattening with little or no impact to the library layout density. We will show results from such a collaboration on IBM