Raymond J. Rosner

Integrated circuit yield management and yield analysis: development and implementation

Integrated circuit manufacturing yields are not necessarily a function of chip area. Accurate yield analysis shows how the yield depends on circuit design and layout. By determining the probabilities of failure and critical areas for different defect types, it is possible to control and manage the yield of integrated circuits. This includes the manufacture of DRAMs, SRAMs, CMOS logic, ASICs, and CMOS and biCMOS microprocessors. Examples explain the method of meeting yield objectives by setting targets for yield components. In addition, the yield management approach allows for a systematic allocation of resources. Required defect-density learning determines the contamination levels for clean rooms and process equipment. >

Yield model for ASIC and processor chips

Yield models based on chip area are inadequate for modeling the yield of CMOS ASIC and processor chips. A model based on the number of circuits was found to give more accurate results. Defect learning curves measured with DRAMs have been used successfully to project the yield of a wide variety of chips.

SRAM Redundancy - Silicon Area versus Number of Repairs Trade-off

In 65nm and smaller technologies, Vmin fails account for a substantial portion of the total fails seen in memories. Redundancy has traditionally been used to fix random point defects which can be modeled with Critical Area Analysis. As technologies migrate from 90 nm to 65nm, cost optimization requires consideration of Vmin yield fallout as well as random defects when selecting a SRAM memory redundancy scheme. Since added redundancy requires additional silicon area, redundancy schemes need to be balanced against the cost required to enable memory repairs.

Wafer line productivity optimization in a multi-technology multi-part-number fabricator

Successful semiconductor manufacturing is driven by wafer-level productivity. Increasing profits by reducing manufacturing cost is a matter of optimizing the factors contributing to wafer productivity. The major wafer productivity components are chips per wafer (CPW), wafer process or fabricator yield (WPY) and wafer final test (WFT) or functional yield. CPW is the count of product chips fitting within the useable wafer surface, and is dependent upon the chip size, dicing channel (kerf) space, and wafer-field size. WPY yield is the percentage of wafers successfully exiting the line; losses include scrap for broken wafers and failed-wafer specifications. WFT yield is the percent of chips that meet all final parametric functional electrical test specifications. Thus, the total wafer level productivity (GCPW) is described by GCPW=CPW/spl middot/WPY/spl middot/WFT. IBMs Vermont fabricator is one of the few in the industry that manufactures DRAMs, SRAMs, microprocessors, ASICs, custom logic, mixed signal, and foundry products, all on the same production floor. The product portfolio spans 12 base technologies across four photolithographic generations from 0.8 /spl mu/m to 0.225 /spl mu/m, with development of 0.18 /spl mu/m. This also encompasses 40 major process flows and over 4000 active part numbers. Such staggering complexity has motivated IBM to consider all possible optimization of these productivity components. This paper describes some of the techniques that have been deployed to achieve this goal.

High-Value Design Techniques for Mitigating Random Defect Sensitivities

Todays sophisticated design-for-manufacturability (DFM) methodologies provide a designer with an overwhelming amount of choices, many with significant costs and unclear value. The technology challenges of subwavelength lithography, new materials, device types/sizes, etc., can mask the underlying random defect yield contribution which ultimately dominates mature manufacturing, and the distinction between technology limitations and process excursions must also be understood. The best DFM strategy fully exploits all of the available techniques that mitigate a designs sensitivity to random defects where the value is clearly quantifiable, yet few designers seize this opportunity. This paper provides a roadmap through the entire design flow and gives an overview of the various options.