Pia N. Sanda

Soft-error resilience of the IBM POWER6 processor

The error detection and correction capability of the IBM POWER6™ processor enables high tolerance to single-event upsets. The soft-error resilience was tested with proton beam- and neutron beam-induced fault injection. Additionally, statistical fault injection was performed on a hardware-emulated POWER6 processor simulation model. The error resiliency is described in terms of the proportion of latch upset events that result in vanished errors, corrected errors, checkstops, and incorrect architected states.

Fault-Tolerant Design of the IBM Power6 Microprocessor

The IBM Power6 microprocessor extends the capabilities of the Power5, dramatically increasing its ability to recover from hard and soft errors without increasing system downtime. The Power6 adds new mainframe-like features for enhanced reliability, availability, and serviceability, including instruction retry and processor failover. Optimized for performance and power, the Power6 implements these RAS enhancements without compromising ultrahigh-frequency operation.

Statistical Fault Injection

A method for statistical fault injection (SFI) into arbitrary latches within a full system hardware-emulated model is validated against particle-beam-accelerated SER testing for a modern microprocessor. As performed on the IBM POWER6 microprocessor, SFI is capable of distinguishing between error handling states associated with the injected bit flip. Methodologies to perform random and targeted fault injection are presented.

Diagnosis and characterization of timing-related defects by time-dependent light emission

Technological advances such as flip-chip packaging, multiple hierarchical wiring planes, and ultra-high frequencies reduce the effectiveness of conventional diagnostic techniques. It has recently been demonstrated that light pulses emitted during circuit switching can be used to characterize the behaviour of integrated circuits. In this paper, a new method of circuit characterization using this technique is described. An example of the diagnosis of a timing failure caused by a resistive path to a single transistor is described.

Cross-layer resilience challenges: metrics and optimization

With increasing sources of disturbances in the underlying hardware, a key challenge in design of robust systems is to meet user expectations at required cost. Cross-layer resilience techniques, implemented across multiple layers of the system stack and designed to work together, can help system designers build effective robust systems at the desired cost point. This paper brings to the forefront two major cross-layer resilience challenges: 1. Quantification and validation of the effectiveness of a cross-layer resilience approach to robust system design in overcoming hardware reliability challenges. 2. Global optimization of a robust system design using cross-layer resilience techniques.

Phaser: phased methodology for modeling the system-level effects of soft errors

This paper presents an overview of Phaser, a toolset and methodology for modeling the effects of soft errors on the architectural and microarchitectural functionality of a system. The Phaser framework is used to understand the system-level effects of soft-error rates of a microprocessor chip as its design evolves through the phases of preconcept, concept, high-level design, and register-transfer-level design implementation. Phaser represents a strategic research vision that is being proposed as a next-generation toolset for predicting chip-level failure rates and studying reliability-performance tradeoffs during the phased design process. This paper primarily presents Phaser/M1, the early stage of the predictive modeling of behavior.

Transmission line pulse picosecond imaging circuit analysis methodology for evaluation of ESD and latchup

This paper will demonstrate the synthesis of the high current pulse source method (e.g. used in transmission line pulse (TLP) systems) and the Picosecond Imaging Circuit Analysis (PICA) tool for the evaluation. of electrostatic discharge (ESD) and latchup phenomenon. In this fashion, the evolution of ESD and latchup can be evaluated in semiconductor devices, and in peripheral circuits at a wafer level or product level. The methodology described in this publication allows for visualization of ESD and latchup, events (e.g. animation in a picosecond time regime). The synthesis of the transmission line pulse (TLP) method and the PICA method allows for the extension of the ESD TLP methodology to terminal currents and spatial and time domain analysis for electrical characterization and reliability analysis, and the high current pulsed source extends the utilization of the PICA methodology for failure analysis on wafer and chip levels.

Picosecond imaging circuit analysis of the POWER3 clock distribution

Picosecond imaging circuit analysis (PICA) is shown to be a valuable means for measuring internal timing of microprocessors operating at speed. In this paper, PICA is applied to the analysis of delays and skew of the IBM POWER3 64b microprocessor clock distribution.

Soft-error resilience of the IBM POWER6 processor input/output subsystem

The soft-error resilience of the IBM POWER6™ processor I/O (input/output) subsystem was measured using proton beam irradiation to accelerate the effect of single-event upsets. Test programs exercised each of the adapters on the chip. Error rates were measured for various cases ranging from idle to high I/O bandwidth and utilization. The POWER6 processor and I/O hub subsystem work together to maintain resiliency even under strenuous irradiation conditions.

The attack of the "Holey Shmoos": a case study of advanced DFD and picosecond imaging circuit analysis (PICA)

This paper will provide a case study of a particularly difficult debug problem (the Holey Shmoo problem) which developed while designing the IBM System/390 G6 637 MHz microprocessor chip. Resolution of this problem involved the use of some of todays newest DFD/DFT and diagnostics techniques. The discussion of the Holey Shmoo problem and its debug will serve to highlight and demonstrate some of these advanced techniques.