Moyra K. McManus

Diagnosis and characterization of timing-related defects by time-dependent light emission

Technological advances such as flip-chip packaging, multiple hierarchical wiring planes, and ultra-high frequencies reduce the effectiveness of conventional diagnostic techniques. It has recently been demonstrated that light pulses emitted during circuit switching can be used to characterize the behaviour of integrated circuits. In this paper, a new method of circuit characterization using this technique is described. An example of the diagnosis of a timing failure caused by a resistive path to a single transistor is described.

Testing and diagnostics of CMOS circuits using light emission from off-state leakage current

In recent years, innovative applications based on the detection of emission sources such as the light emission from off-state leakage current (LEOSLC) of CMOS transistors have been developed for testing and diagnosing modern ultralarge-scale integration circuits. In this paper, we show that LEOSLC can be used to effectively debug circuits, localize defects with a quick turn around time, read the logic state of gates, and extract the internal voltage drop of power distribution grids among others.

Model-based guidelines to suppress cable discharge event (CDE) induced latchup in CMOS ICs

An analytical model has been developed to provide physical design guidelines to suppress CDE-induced latchup in CMOS ICs. The design guidelines implemented in two test chips in IBMs 130nm technology successfully suppressed latchup against transient pulses of up to 6A peak current and against DC current pulses (EIA/JESD 78 test) of +/- 400mA.

Diagnostic techniques for the IBM S/390 600 MHz G5 microprocessor

This paper describes strategies and techniques used to diagnose failures in the IBM 600 MHz G5 (Generation 5) CMOS microprocessor and associated cache chips. Time-to-market pressure demands quick diagnostic turnaround time while the complexity, density, cycle time, and technology issues of the hardware increase the difficulty of diagnosis. Since G5 first silicon, intense diagnostics and physical failure analysis (PFA) have successfully identified the root cause of many failures, including examples of process, design, and random manufacturing defects. This success is attributed to the three techniques described in this paper. For each technique, an example is presented to demonstrate its effectiveness.

Transmission line pulse picosecond imaging circuit analysis methodology for evaluation of ESD and latchup

This paper will demonstrate the synthesis of the high current pulse source method (e.g. used in transmission line pulse (TLP) systems) and the Picosecond Imaging Circuit Analysis (PICA) tool for the evaluation. of electrostatic discharge (ESD) and latchup phenomenon. In this fashion, the evolution of ESD and latchup can be evaluated in semiconductor devices, and in peripheral circuits at a wafer level or product level. The methodology described in this publication allows for visualization of ESD and latchup, events (e.g. animation in a picosecond time regime). The synthesis of the transmission line pulse (TLP) method and the PICA method allows for the extension of the ESD TLP methodology to terminal currents and spatial and time domain analysis for electrical characterization and reliability analysis, and the high current pulsed source extends the utilization of the PICA methodology for failure analysis on wafer and chip levels.

The attack of the "Holey Shmoos": a case study of advanced DFD and picosecond imaging circuit analysis (PICA)

This paper will provide a case study of a particularly difficult debug problem (the Holey Shmoo problem) which developed while designing the IBM System/390 G6 637 MHz microprocessor chip. Resolution of this problem involved the use of some of todays newest DFD/DFT and diagnostics techniques. The discussion of the Holey Shmoo problem and its debug will serve to highlight and demonstrate some of these advanced techniques.

Design for low power and power management in IBM Blue Gene/Q

In this paper, we explain the techniques used in IBM Blue Gene®/Q Compute chips to achieve high energy efficiency. Architectural techniques include the choice of a power-efficient, throughput-oriented processor core with a SIMD (single-instruction, multiple-data) floating-point unit, as well as multiple frequency domains for moving data. Design techniques include clock gating and the use of multiple threshold voltage devices. From a systems perspective, power is reduced by using a speed binning technique that characterizes the manufacturing variability of chips during wafer test, permitting similar chips to be packaged on the same board and run at the lowest voltage possible. We describe the techniques used to monitor and manage the power and performance of the various subunits of the Blue Gene/Q chip. Details include the functioning of the environmental monitor and the performance counters. Using these facilities, we describe the framework to understand how the chips subunits contribute to the total active and leakage power consumed. A power characterization technique for the development of application-dependent power projection models is presented. Differences between estimated power before chip tape-out versus measured power are discussed.

An advanced optical diagnostic technique of IBM z990 eServer microprocessor

In this paper, we describe an advanced optical diagnostic technique used for diagnosing the IBM z990 eServer microprocessor (Slegel et al., 2004). Time-to-market pressure demands quick diagnostic turnaround time and high diagnostic resolution while the ever increasing design complexity, density, cycle time, and shrinking technologies dramatically add difficulties to diagnostics. Although design-for-test (DFT) and design-for-diagnostics (DFD) features are implemented in the latest microprocessors to help easing the diagnostic efforts, they may still not be sufficient to diagnose certain fails. The well-known picosecond imaging circuit analysis (PICA) (Kash and Tsang, 1997) tool, equipped with the high quantum efficiency superconducting single-photon detector (SSPD,) shows a unique diagnostic capability for optically probing the internal nodes of a chip. Several hard-to-diagnose examples will be used to demonstrate the unique capabilities of this technique

Optical and electrical testing of latchup in I/O interface circuits

Backside light emission and electrical measurements were used to evaluate the susceptibility to latchup of externally cabled I/O pins for a 0.13 µm technology generation [1,2] test chip, which was designed in a flip-chip package. Case studies of several Inputs/Outputs (I/Os) are shown along with conclusions regarding layout and floorplanning to ensure the robustness to various types of latchup trigger events.

Timing high-speed microprocessor circuits using picosecond imaging circuit analysis

IBM Research has developed a time resolved imaging technique, Picosecond Imaging Circuit Analysis (PICA), which uses single photon events to analyze signals in modern microprocessors on a picosecond time scale. This paper will describe the experimental setup as well as the data management software. A case study of a particularly hard debug problem on a state of the art microprocessor will demonstrate the application of the PICA method.