David P. Vallett

Picosecond imaging circuit analysis

A newly developed optical method for noninvasively measuring the switching activity of operating CMOS integrated circuit chips is described. The method, denoted as picosecond imaging circuit analysis (PICA) can be used to characterize the gate-level performance of such chips and identify the locations and nature of their operational faults. The principles underlying PICA and examples of its use are discussed.

IC failure analysis: the importance of test and diagnostics

Continuous improvements in yield, reliability, time to market, and customer satisfaction all benefit from quick corrective action through root-cause failure analysis. The author reviews software- and hardware-based diagnostic methods for fault localization, the first and most critical step in this process.

Diagnosis and characterization of timing-related defects by time-dependent light emission

Technological advances such as flip-chip packaging, multiple hierarchical wiring planes, and ultra-high frequencies reduce the effectiveness of conventional diagnostic techniques. It has recently been demonstrated that light pulses emitted during circuit switching can be used to characterize the behaviour of integrated circuits. In this paper, a new method of circuit characterization using this technique is described. An example of the diagnosis of a timing failure caused by a resistive path to a single transistor is described.

Time-resolved optical characterization of electrical activity in integrated circuits

If the rate of improvement in the performance of advanced silicon integrated circuits is to be sustained, new techniques for the measurement of electrical waveforms in operating circuits are needed. Critical factors dictating this requirement include the increased speed and complexity of circuits, the growing importance of faults that appear only during high-speed operation, and the use of flip-chip packaging technologies. Two recently developed all-optical methods for measuring the switching activity from the backside of a chip are described and compared. One is a passive approach based on the measurement of hot carrier luminescence emitted from the channel of a CMOS field-effect transistor (FET) during switching. The second uses a laser probe to sense the switching induced modulation of the silicon optical constants near an FETs source and drain.

An overview of CMOS VLSI failure analysis and the importance of test and diagnostics

This paper reviews the logic failure analysis process and the critical need for design-for-diagnostics. The use of flip-chip packaging will render hardware-based diagnostic techniques from the front side of the die obsolete, e.g., liquid crystal, electron beam testing, and photon emission microscopy. Two primary solutions are discussed: software-based diagnostic methods, e.g., scan, and the adaptation of hardware techniques to the backside of the die.

Failure analysis requirements for nanoelectronics

Failure analysis (FA) plays a vital role in the development and manufacture of integrated circuits (ICs). But instrumental limits are already threatening FA in the tenth-micron CMOS realm, and nanoelectronic scale devices will find key analytical tools two orders of magnitude removed in capability. This paper will introduce state of the art microelectronic failure analysis processes, instrumentation, and principles. It will discuss the major limitations and future prospects projected using industry roadmaps. Specifically highlighted is the need for fault isolation methodology for failure analysis of fully integrated nanoelectronics devices.

Finding fault with deep-submicron ICs

The ability to isolate and identify subtle defects on complex chips is threatened as semiconductor technology approaches the tenth-micron realm.

Why Waste Time on Roadmaps When We Don't Have Cars?

Reliability and yield depend on timely accurate failure analysis (FA). While scaling and new materials continue to drive integrated circuit performance, key areas of analytical technology remain largely stagnant. FA roadmaps and whitepapers detail major challenges facing the industry, but research, development, and tool commercialization are languid. Unlike the mainstream activities of design, manufacturing, and test, FA suffers from a loss of focus, a lack of funding, and a small commercial market. After a review of major shortcomings in analytical capability, this paper will discuss barriers to analytical technology development and propose alternatives for providing a more fertile infrastructure for requisite research and development.

FA Future Requirements

Failure analysis, like any facet of the semiconductor industry, is challenged to continuously improve to remain viable. Consider a microprocessor in the year 2006, operating at only 3 GHz, a full 500 mHz below its specified clock frequency of 3.5 gHz. Somewhere in its 200,000,000 transistors, each with a gate dielectric 1.5–2 nm thick (about 3 silicon atom spacings), buried in 7 levels and 5000 meters of metal wiring and 4000 area-array solder balls, is a single defect, perhaps an area of chemical contamination in the air-filled dielectric. It causes a slight increase in capacitance between two conductors and a circuit delay of just 2–3 ps. The contamination is invisible in an optical or electron microscope and below the detection limits of current scanning probe techniques. It is easily removed during deprocessing of the dielectric film. The IC is flip-chip mounted directly to a printed circuit board and must be exercised in-place to recreate the failure. The use of built-in diagnosability is limited and the design is highly synthesized, restricting understanding of circuit operation.