Daniel W. Storaska

A 28-Gb/s 4-Tap FFE/15-Tap DFE Serial Link Transceiver in 32-nm SOI CMOS Technology

As exemplified by standards such as OIF CEI-25G, 32G-FC, and next-generation 100GbE, serial link data rates are being pushed up to 25 to 28Gb/s in order to increase I/O system bandwidth. Such speeds represent a near doubling of the state-of-the-art for fully integrated transceivers [1-3]. With scaling no longer providing large gains in device speed, significant design advances must be made to attain these data rates. This paper describes a 28Gb/s serial link transceiver featuring a source-series terminated (SST) driver topology with twice the speed of existing designs, a two-stage peaking amplifier with capacitively-coupled parallel input stages and active feedback, and a 15-tap DFE. The use of capacitive level-shifters allows a single current-integrating summer to drive the parallel paths used for speculating the first two DFE taps.

10+ gb/s 90-nm CMOS serial link demo in CBGA package

We report a 10+ Gb/s serial link demo chip with NRZ signaling in 90-nm CMOS. It consists of a full-rate 4:1 MUX with 8-tap feed-forward equalizer, a half-rate 1:4 DEMUX with programmable peaking pre-amplifier, and a parallel port interface. All coefficients of the 8-tap FIR filter have programmable polarity and magnitude. The chip is housed in CBGA package and has ESD protection devices on all pins. All clock signals are supplied externally. The measured maximum speeds of stand-alone transmitter and receiver are 11.7 Gb/s and 13.3 Gb/s, respectively, and maximum back-to-back operation speed (transmitter + receiver) is 11.4 Gb/s. The chip operates at 10 Gb/s over 20 ft of lossy cable with 20 dB attenuation at 5 GHz. All circuits in the chip use a single 1.0 V power supply, except TX output driver and RX input termination network, which use 1.4 V supply. Total power consumption of TX and RX from the two supplies is 280 mW.

A 32 Gb/s Backplane Transceiver With On-Chip AC-Coupling and Low Latency CDR in 32 nm SOI CMOS Technology

This paper describes key design features of a 32 Gb/s 4-tap FFE/15-tap DFE transceiver in 32 nm SOI CMOS which mitigate major sources of degradation in transceiver performance. The transceiver employs a passive feed-forward restore (FFR) scheme in an on-chip AC-coupling network to prevent pattern-dependent baseline wander, a low-latency clock and data recovery (CDR) to improve high-frequency jitter tolerance, and a token-based power management scheme to reduce supply ripple. At 32 Gb/s, the transceiver can equalize a channel with 30 dB of loss at a bit-error rate below 10-12 while consuming 21 mW/Gbps at 1 V supply and an area of 0.7 mm2.

10+ Gb/s 90nm CMOS serial link demo in CBGA package

We report a 10+ Gb/s serial link demo chip in 90-nm CMOS. It consists of a full-rate 4:1 MUX with 8-tap feed-forward equalizer, a half-rate 1:4 DEMUX with programmable peaking pre-amplifier, and a parallel port interface. The chip is housed in CBGA package and uses ESD devices on all pins. The measured maximum speed of stand-alone transmitter and receiver was 11.7 Gb/s and 13.3 Gb/s respectively, and maximum back-to-back operation speed (transmitter+receiver) was 11.4 Gb/s.

A 32-Gb/s backplane transceiver with on-chip AC-coupling and low latency CDR in 32-nm SOI CMOS technology

This paper describes key design features of a 32-Gb/s 4-tap FFE/15-tap DFE transceiver in 32-nm SOI CMOS which mitigate major sources of degradation in transceiver performance. The transceiver employs a passive feed-forward restore (FFR) scheme in an on-chip AC-coupling network to prevent pattern-dependent baseline wander, a low latency clock and data recovery (CDR) to improve high frequency jitter tolerance, and a token-based power management scheme to reduce supply ripple. The transceiver can equalize a channel with 30dB of loss at a bit-error rate below 10-12 while using 21 mW/Gbps at 1V supply and 0.7 mm2.