Daniele Cantarelli

Failure mechanisms of flash cell in program/erase cycling

The impact of program/erase cycling on flash memory cell is reviewed considering both performance degradation of the typical bit and the evolution of the erase threshold voltage distribution of the whole memory array. Emphasis is given to the failure mechanisms which affect flash memory endurance: the erratic erase phenomenon is discussed with reference to the model recently reported in the literature and a new degradation mechanism, induced by parasitic drain stress conditions in program/erase cycling, is presented.<<ETX>>

Experimental transient analysis of the tunnel current in EEPROM cells

Since the cell is written with a ramp waveform pulse in order to minimize the maximum tunnel current in actual device operation, the measurements were performed with ramp waveform writing pulses at different ramp speeds. The kind of information obtained from the transient analysis greatly improves the understanding of the device physics. By measuring tunnel current, some expected results, such as the dependence of the maximum current value on the ramp speed, were observed. Some unexpected results, such as an anomalous peak during the erasing operation and the influence of the ramp speed on the conduction properties of the thin oxide, which is shown by the Fowler-Nordheim plot of the experimental tunnel current, were also observed. >

A novel method for the experimental determination of the coupling ratios in submicron EPROM and flash EEPROM cells

A novel method for evaluating the coupling ratios alpha /sub G/ and alpha /sub D/ of hot-electron programmable memory cells has been developed. The evaluation is based only on measurements performed on the cell and does not rely on the comparison of the cell with the equivalent MOS transistor. The sensitivity to slight differences between the two structures, which becomes more severe as the scaling-down continues, is thus eliminated. The method allows the coupling ratios to be determined also in those new high-density memory array designs in which it is impossible to obtain the equivalent transistor. The method has been validated on a 0.8 mu m technology EPROM and on a 1.0 mu m technology flash-EEPROM.<<ETX>>

Complete transient simulation of flash EEPROM devices

It has been demonstrated that the Fowler-Nordheim tunneling, hot electron injection, and band-to-band tunneling current models incorporated into the 2D device simulator HFIELDS have allowed an accurate simulation and analysis of the flash EEPROM cell during the transient writing cycles. These represent all the important physical mechanisms which occur during the writing of flash EEPROM devices. The physical models have been verified by comparison with flash EEPROM devices fabricated using a 1.0 mu m technology.<<ETX>>

Analyzing integrated circuits at work with a picosecond time-gated imager

A system based on a picosecond time-gated image intensifier is proposed for non-contact testing of CMOS circuits. The apparatus allows one to record the temporal evolution of the luminescence emitted during transistor switching as a function of the position inside the chip. The system is characterized by an intrinsic parallelism in the spatial dimensions. This feature is noticeable for studying wide sections of complex circuits, like microprocessors and random access memories, where multiple electrical events occur simultaneously. Experiments on a CMOS inverter chain and on a static memory have been carried out, in order to demonstrate the applicability of a picosecond time-gated imager to circuit analysis.