Lorenzo Fratin

Failure mechanisms of flash cell in program/erase cycling

The impact of program/erase cycling on flash memory cell is reviewed considering both performance degradation of the typical bit and the evolution of the erase threshold voltage distribution of the whole memory array. Emphasis is given to the failure mechanisms which affect flash memory endurance: the erratic erase phenomenon is discussed with reference to the model recently reported in the literature and a new degradation mechanism, induced by parasitic drain stress conditions in program/erase cycling, is presented.<<ETX>>

Application of advanced ion implantation techniques to Flash memories

Abstract Flash memories have become the most important of non-volatile memories because of their potential application as mass storage devices in portable computers. The evolution of Flash memory technology is oriented to both reducing cell size and up-grading product functions. Significant modifications of the structure and the operating modes of memory cell as well as innovative CMOS process architectures are needed for next generations of Flash memories. An important contribution to the evolution of Flash technology comes from the implementation of advanced ion implantation techniques; the role of large angle tilted implantation and of high energy implantation is illustrated showing most relevant applications in relation with the improvements of device structure and performance.

Electrical characterization and reliability of double-doped drain MOS transistors compatible with an EEPROM process☆

Abstract Double-doped drain/source (As-P) n-MOS transistors with gate-drain and gate-source overlapping have been manufactured within a standard CMOS EEPROM process. Owing to a decrease in the longitudinal electric field, and the enhanced control of the gate on the low doped drain region, both snap-back voltage and hot electron effects are markedly reduced, allowing reliable operation at high drain voltages at the expense of a tolerable increase in drain, source/gate capacitances. Devices have been submitted to a hot electron accelerated test at V ds = 10 V , V gs = 5 V . The observed degradation seems to be mainly due to acceptor-type interface state creation near the drain junction.