Vasileios Tenentes

Single and Variable-State-Skip LFSRs: Bridging the Gap Between Test Data Compression and Test Set Embedding for IP Cores

Even though test set embedding (TSE) methods offer very high compression efficiency, their excessively long test application times prohibit their use for testing systems-on-chip (SoC). To alleviate this problem we present two new types of linear feedback shift registers (LFSRs), the Single-State-Skip and the Variable-State-Skip LFSRs. Both are normal LFSRs with the addition of the State-Skip circuit, which is used instead of the characteristic-polynomial feedback structure for performing successive jumps of constant and variable length in their state sequence. By using Single-State-Skip LFSRs for testing single or multiple identical cores and Variable-State-Skip LFSRs for testing multiple non-identical cores we get the well-known high compression efficiency of TSE with substantially reduced test sequences, thus bridging the gap between test data compression and TSE methods.

State skip LFSRs: bridging the gap between test data compression and test set embedding for IP cores

We present a new type of linear feedback shift registers, state skip LFSRs. state skip LFSRs are normal LFSRs with the addition of a small linear circuit, the State Skip circuit, which can be used, instead of the characteristic-polynomial feedback structure, for advancing the state of the LFSR. In such a case, the LFSR performs successive jumps of constant length in its state sequence, since the State Skip circuit omits a predetermined number of states by calculating directly the state after them. By using State Skip LFSRs we get the well- known high compression efficiency of test set embedding with substantially reduced test sequences, since the useless parts of the test sequences are dramatically shortened by traversing them in state skip mode. The length of the shortened test sequences approaches that of test data compression methods. A systematic method for minimizing the test sequences of re- seeding-based test set embedding methods, and a low overhead decompression architecture are also presented.

Defect aware X-filling for low-power scan testing

Various X-filling methods have been proposed for reducing the shift and/or capture power in scan testing. The main drawback of these methods is that X-filling for low power leads to lower defect coverage than random-fill. We propose a unified low-power and defect-aware X-filling method for scan testing. The proposed method reduces shift power under constraints on the peak power during response capture, and the power reduction is comparable to that for the Fill-Adjacent X-filling method. At the same time, this approach provides high defect coverage, which approaches and in many cases is higher than that for random-fill, without increasing the pattern count. The advantages of the proposed method are demonstrated with simulation results for the largest ISCAS and the IWLS benchmark circuits.

Defect-Oriented LFSR Reseeding to Target Unmodeled Defects Using Stuck-at Test Sets

Defect screening is a major challenge for nanoscale CMOS circuits, especially since many defects cannot be accurately modeled using known fault models. The effectiveness of test methods for such circuits can therefore be measured in terms of the coverage obtained for unmodeled faults. In this paper, we present a new defect-oriented dynamic LFSR reseeding technique for test-data compression. The proposed technique is based on a new output-deviation metric for grading stuck-at patterns derived from LFSR seeds. We show that, compared to standard compression-driven dynamic LFSR reseeding and a previously proposed deviation-based method, higher defect coverage is obtained using stuck-at test cubes without any loss of compression.

High-Quality Statistical Test Compression With Narrow ATE Interface

In this paper, we present a novel compression method and a low-cost decompression architecture that combine the advantages of both symbol-based and linear-based techniques and offer a very attractive unified solution that removes the barriers of existing test data compression techniques. Besides the traditional goals of high compression and short test application time, the proposed method also offers low shift switching activity and high unmodeled defect coverage at the same time. In addition, it favors multi-site testing as requires a very low pin-count interface to the automatic test equipment. Finally, contrary to existing techniques, it provides an integrated solution for testing multi-core system on chips (SoCs) as it is suitable for cores of both known and unknown structures that usually coexist in SoCs.

High Quality Testing of Grid Style Power Gating

This paper shows that existing delay-based testing techniques for power gating exhibit fault coverage loss due to unconsidered delays introduced by the structure of the virtual voltage power-distribution-network (VPDN). To restore this loss, which could reach up to 70.3% on stuck-open faults, we propose a design-for-testability (DFT) logic that considers the impact of VPDN on fault coverage in order to constitute the proper interface between the VPDN and the DFT. The proposed logic can be easily implemented on-top of existing DFT solutions and its overhead is optimized by an algorithm that offers trade-off flexibility between test-application-time and hardware overhead. Through physical layout SPICE simulations, we show complete fault coverage recovery on stuck-open faults and 43.2% test-application-time improvement compared to a previously proposed DFT technique. To the best of our knowledge, this paper presents the first analysis of the VPDN impact on test quality.

Test-data volume and scan-power reduction with low ATE interface for multi-core SoCs

Symbol-based and linear-based test-data compression techniques have complementary properties which are very attractive for testing multi-core SoCs. However, only linear-based techniques have been adopted by industry as the symbol-based techniques have not yet revealed their real potential for testing large circuits. We present a novel compression method and a low-cost decompression architecture that combine the advantages of both symbol-based and linear-based techniques under a unified solution for multi-core SoCs. The proposed method offers higher compression than any other method presented so far, very low shift switching activity and very short test sequence length at the same time. Moreover, contrary to existing techniques, it offers a complete solution for testing multi-core SoCs as it is suitable for cores of both known and unknown structure (IP cores) that usually co-exist in modern SoCs. Finally, it supports very low pin-count interface as it needs only one tester channel to download fast the compressed test data on-chip.

Aging Benefits in Nanometer CMOS Designs

In this brief, we show that bias temperature instability (BTI) aging of MOS transistors, together with its detrimental effect for circuit performance and lifetime, presents considerable benefits for static power consumption due to subthreshold leakage current reduction. Indeed, static power reduces considerably, making CMOS circuits more energy efficient over time. Static power reduction depends on transistor stress ratio and operating temperature. We propose a simulation flow allowing us to properly evaluate the BTI aging of complex circuits in order to estimate BTI-induced power reduction accurately. Through HSPICE simulations, we show 50% static power reduction after only one month of operation, which exceeds 78% in ten years. BTI aging benefits for power consumption are also proven with experimental measurements.

Reliable Power Gating With NBTI Aging Benefits

In this paper, we show that negative bias temperature instability (NBTI) aging of sleep transistors (STs), together with its detrimental effect for circuit performance and lifetime (LT), presents considerable benefits for power-gated circuits. Indeed, it reduces static power due to leakage current, and increases ST switch efficiency, making power gating more efficient and effective over time. The magnitude of these aging benefits depends on operating and environmental conditions. By means of HSPICE simulations, considering a 32-nm CMOS technology, we demonstrate that static power may reduce by more than 80% in 10 years of operation. Static power decrease over time due to NBTI aging is also proven experimentally, using a test chip manufactured with a 65-nm technology. We propose an ST design strategy for reliable power gating, in order to harvest the benefits offered by NBTI aging. It relies on the design of STs with a proper lower Vth compared with the standard STs. This can be achieved by either redesigning the STs with the identified Vth value or applying a proper forward body bias to the available power switching fabrics. Through the HSPICE simulations, we show LT extension up to 21.4× and average static power reduction up to 16.3% compared with the standard ST design approach, without additional area overhead. Finally, we show LT extension and several performance-cost tradeoffs when a target maximum LT is considered.

BTI and leakage aware dynamic voltage scaling for reliable low power cache memories

We propose a novel dynamic voltage scaling (DVS) approach for reliable and energy efficient cache memories. First, we demonstrate that, as memories age, leakage power reduction techniques become more effective due to sub-threshold current reduction with aging. Then, we provide an analytical model and a design exploration framework to evaluate trade-offs between leakage power and reliability, and propose a BTI and leakage aware selection of the “drowsy” state retention voltage for DVS of cache memories. We propose three DVS policies, allowing us to achieve different power/reliability trade-offs. Through SPICE simulations, we show that a critical charge and a static noise margin increase up to 150% and 34.7%, respectively, is achieved compared to standard aging unaware drowsy technique, with a limited leakage power increase during the very early lifetime, and with leakage energy saving up to 37% in 10 years of operation. These improvements are attained at zero or negligible area cost.