Daoqiang Lu

High-Speed Flex-Circuit Chip-to-Chip Interconnects

High-speed chip-to-chip interconnect utilizing flex-circuit technology is investigated for extending the lifetime of copper-based system-level channels. Proper construction of the flex ribbon is shown to improve the raw bandwidth over standard FR-4 boards by about three times. Active testing results from a 130-nm CMOS test vehicle show the potential of up to two times higher data rates. The next-generation test vehicle with 90-nm CMOS circuits gives improved voltage and timing margins at 20 Gb/s. In an interconnect limited case a channel with 36 in (91.4 cm) of flex runs at 18.2 Gb/s data rate at a bit-error ratio (BER) of better than 10-12. The channel includes two 90-nm CMOS test chips, two organic flip-chip package substrates, and two flex connectors; crosstalk is not included in this experiment. High-speed connector solutions, including results from a ldquosplit socketrdquo assembly test vehicle, are discussed in detail. The characterization of two top-side flex connector prototypes demonstrates their basic durability and good high-frequency performance. Samples survive 100 mating cycles at an average contact resistance of less than 30 mOmega, adequate for high-speed signaling. Measured differential insertion loss is less than 1.5 dB up to 10 GHz and less than 3.5 dB up to 20 GHz. Near-end and far-end crosstalk measurements indicate that the connectors exceed crosstalk specifications.

Optical I/O technology for digital VLSI

We describe the development of a high-speed, 12-channel (8-data, 2-clock and 2-alignment channels), parallel optical link with a unique packaging concept. The package is used to demonstrate the viability of chip-to-chip optical I/O in very large scale integration (VLSI) circuits. However, for implementation of optical systems in high performance computing applications, the cost of components and packaging has to come down significantly from the traditional optical communication distances. In the current work we attempted to realize such a system by using power efficient optical and electronic components together with a potentially low cost packaging solution compatible with the electronics industry. Vertical Cavity Surface Emitting Lasers (VCSEL), positive-intrinsic-negative (PIN) photodetectors, polymer waveguide arrays as well as CMOS transceiver chip were heterogeneously integrated on a standard microprocessor flip-chip pin grid array (FCPGA) substrate. The CMOS transceiver chip from 0.18μm processing technology contains VCSEL drivers, transimpedance and limiting amplifiers and on-chip self-testing circuits. A self-test circuit in such high-speed systems will be highly beneficial to reduce the testing cost in real products. For fully assembled packages we measured a 3 Gb/s optical eye for the transmitter (24Gb/s aggregate data rate) and a transmission over the complete link was achieved at 1 Gb/s (8Gb/s aggregate data rate).

Optical hybrid package with an 8-channel 18GT/s CMOS transceiver for chip-to-chip optical interconnect

We describe the design and development of a high-speed 8-channel hybrid integrated optical transceiver package with Clock and Data Recovery (CDR) circuits. The package concept has been developed to be compatible with microprocessor package technology and at the same time allow the integration of low cost, high-performance optical components. A 90nm CMOS optical transceiver chip, 850nm 10Gb/s GaAs based vertical cavity surface emitting laser (VCSEL) array and PIN photodiode array are flip-chip mounted on a standard microprocessor Land Grid Array (LGA) package substrate. The CMOS drivers and receivers on the transceiver chip and the optical components (VCSEL and Photodiode arrays) are electrically coupled using a short transmission line routed on the top surface of the package. VCSEL and photodiode arrays are optically coupled to on-package integrated polymer waveguide arrays with metallized 45° mirrors. The waveguides, which are terminated with multi-terminal (MT) fiber optic connectors, couple out/in high-speed optical signals to/from the chip. The CMOS transceiver chip fully integrates all analog optical circuits such as VCSEL drivers, transimpedance amplifiers and clock and data recovery (CDR) retiming circuit with a low jitter LC-PLL. Digital circuits for pseudorandom bit-pattern sequence generators (PRBS) and bit-error rate test (BERT) are fully integrated. 20Gb/s electrical and 18Gb/s optical eye diagrams for the transmitter were measured out of the package. A fully packaged transmitter and receiver including clock data recovery at 10Gb/s have also been measured.