Daquan Yu

Electromigration performance of Through Silicon Via (TSV) – A modeling approach

The electromigration (EM) performance of Through Silicon Via (TSV) in silicon interposer application are studied using Finite Element (FE) modeling. It is found that thermo-mechanical stress is the dominant contribution factor to EM performance in TSV instead of the current density. The predicted failure site is dependent on the process technology, and exhibits asymmetric behavior if different process is used between the top and bottom metallization of a TSV. Modeling is also done for two different coverage patterns of top metallization, namely (i) the metal line covers the via completely, and (ii) the metal line only extends to the centre of the via, covering half of the via. The simulation results of the latter model show the existence of a second EM failure site and worse EM performance is expected. This additional possible EM failure site is further confirmed through dynamic simulation of void growth.

Study of 15µm pitch solder microbumps for 3D IC integration

Developments of ultra fine pitch and high density solder microbumps and assembly process for low cost 3D stacking technologies are discussed in this paper. The solder microbumps developed in this work consist of Cu and Sn, which are electroplated in sequential with total thickness of 10µm; The under bump metallurgy (UBM) pads used here is electroless plated nickel and immersion gold (ENIG) with thickness of 2µm. Accordingly, joining of the two Si chips can be conducted by joining CuSn solder microbumps to ENIG UBM pads or CuSn solder microbumps to CuSn solder microbumps. The first joining can only be done with chip to chip assembly whereas the second joining has the potential for chip to wafer assembly. Assembly of the Si chips is conducted with the FC150 flip chip bonder at different temperatures, times, and pressures and the optimized bonding conditions are obtained. After assembly, underfill process is carried out to fill the gap and a void free underfilling is achieved using an underfill material with fine filler size.

Development of Fine Pitch Solder Microbumps for 3D Chip Stacking

Developments of ultra fine pitch and high density solder microbumps for advanced 3D stacking technologies are discussed in this paper. CuSn solder microbumps with 25 ¿m in pitch are fabricated at wafer level by electroplating method and the total thicknesses of the platted Cu and Sn are 10 ¿m. After plating, the micro bumps on the Si chip are reflowed at 265°C and the variation of bump height measured within a die is less than 5%. The under bump metallurgy (UBM) layer on the Si carrier used is electroless plated nickel and immersion gold (ENIG) with total thickness less than 5 ¿m. Assembly of the Si chip and the Si carrier is conducted with the FC150 flip chip bonder at different temperatures, times, and pressures and the optimized bonding conditions are obtained. After assembly, underfill process is carried out to fill the gap and a void free underfilling is achieved using an underfill material with fine filler size.

Electromigration study of 50 µm pitch micro solder bumps using four-point Kelvin structure

Electromigration (EM) of micro bumps of 50 µm pitch was studied using four-point Kelvin structure. Two kinds of bumps, i. e., SnAg solder bump and Cu post with SnAg solder were tested. These bumps with thick Cu under bump metallization (UBM) were bonded with electroless Ni/Au (ENIG) pads. The results showed different EM features comparing with larger flip chip joints. Under various test temperatures from 100 to 140 °C, the increasing of electrical resistance under current stressing was mainly due to the formation of the high temperature intermetallic compounds (IMCs). The resistance increase-rate in solder bump interconnects was faster than that of Cu post with SnAg bump joints since there was more low temperature solder and under current stressing, more IMCs would be formed. When Cu post with SnAg bumps were tested at 140 °C with the current density of 4.08×104 A/cm2, after certain stressing time the resistances would reach a plateau region, where the diffusion between different materials, i. e., Cu, Ni and Sn reached equilibrium, and IMCs became stable. Large number of Kirkendall voids and a number of cracks were found in the Cu post interconnects which was caused by the electron wind since less voids and cracks were found in the adjacent bump interconnects. When Cu post with SnAg bumps were tested at 140 °C with the current density of 2.04×104 A/cm2 for 1000 h, the resistance did not reach steady state. The electron flow direction also has an effect on the diffusion of materials. The degradation of resistance increased faster when electrons flow from Cu UBM to ENIG.

Development of low temperature bonding using in-based solders

In-based solders were chosen for the low temperature bonding at lower than 180degC. Three kinds of bonding types on Au/Cu/Ti/SiO2/Si dies, which were Sn/In and Au/In for Type 1, Au/In and Au/Sn for Type 2, and InSn alloy and InSn alloy for Type 3, were studied expecting that the whole In- solder layer is converted to the mixed intermetallic compound (IMC) phases of In-Cu and In-Au IMCs after bonding below 180degC and annealing at 100~120degC. The IMC in the joints were characterized in terms of the micro structure observations and the compositional analysis with Scanning Electron Microscopy (SEM) and Energy Dispersive X-ray Spectroscopy (EDX), the phase identification with X-ray Diffraction (XRD) and the re-melting temperature with Differential Scanning Calorimetry (DSC). The phase equilibriums of the joints were examined by thermodynamic calculations to understand the re-melting behavior. As a result, complete bonding consisted of only high melting temperature IMCs, Cu11ln9, Cu2In, eta-Cu6Sn5, and Auln2, was successfully made at 120degC followed by annealing at 100degC in Type 3, and at 160degC with annealing for lOhrs or at 180degC without annealing for Type 1, which was confirmed by DSC measurements and explained through thermodynamic calculations.

The role of Ni buffer layer on high yield low temperature hermetic wafer bonding using In/Sn/Cu metallization

Low temperature hermetic wafer bonding using In/Sn interlayer and Au/Ni/Cu metallization as the high-melting-point (HMP) components was reported, wherein the thin Ni layer was introduced as a buffer layer to prevent solder consumption after their deposition. 8 in. wafer to wafer bonding was achieved at 180 °C for 20 min under 5.5 Mpa. Voids free seal joints composed of high temperature intermetallic compounds were obtained with good hermeticity. Present results show that the buffer layer is the key to ensure high yield hermetic wafer bonding when the low-melting-point solder was deposited directly on the HMP component.

Effect of thermal annealing on TSV Cu protrusion and local stress

Through silicon vias (TSVs) are regarded as one of the key enabling component to achieve three-dimensional (3D) integrated circuit (IC) functionality. In this paper, we present the investigation on TSV protrusion and stress at different annealing conditions tested by means of optical profiler and high efficiency micro-Raman microscopy. Finite element method is utilized to model and simulate the thermo-mechanical behavior of the TSV having a diameter of 20 μm and a depth of 120 μm under different annealing temperatures. The measured protrusion increases with annealing temperature below 400°C, and then decreases when being further annealed. The maximum measured silicon stress as a function of annealing temperature has shown similar trend to the protrusion. The pre-annealing has limited effect on protrusion, but is helpful to reduce the silicon stress.

Assembly and reliability of micro-bumped chips with Through-silicon Vias (TSV) interposer

This paper presents the assembly optimization and charcterierization of Through-Silicon Vias (TSV) interposer technology for two 8 × 10mm2 micro-bumped chips. The two micro-bumped chips represent different functional dies in a System-in-package (SiP). In the final test vehicle, one of the micro-bumped chips had 100μm bump pitch and 1,124 I/O; the other micro-bumped chip had 50μm bump pitch and 13,413 I/O. The TSV interposer size is 25 × 25 × 0.3mm3 with CuNiAu as UBM on the top side and SnAgCu bumps on the underside. The conventional substrate size is 45 × 45mm2 with 1-2-1 layer configuration, a ball-grid array (BGA) of 1mm pitch and a core thickness of 0.8mm. The final test vehicle was subjected to MSL3 and TC reliability assessment. The objective of this paper was to incorporate two 8 × 10mm2 micro-bumped chips into TSV interposer. The micro-bumped chips should have no underfill voiding issue and the whole package should be able to pass Moisture Sensitivity Level 3 (MSL3) and Thermal Cycling (TC) reliability assessment. To achieve this objective of incorporating micro-bumped chips into the TSV interposer, the challenges were small standoff height/ low bump pitch of the micro-bumped chip, underfill flowability and its reliability performance. To overcome these challenges, different types of capillary flow underfill, bump layout designs and bump types were evaluated and a quick reliability assessment was used to select the materials and test vehicle parameters for final assembly and reliability assessment.

Wafer-Level Hermetic Bonding Using Sn/In and Cu/Ti/Au Metallization

Low-temperature hermetic wafer bonding using In/Sn interlayer and Cu/Ti/Au metallization was investigated for microelectromechanical systems packaging application. In this case, the thin Ti layer was used as a buffer layer to prevent the diffusion between solder interlayer and Cu after deposition and to save more solders for diffusion bonding process. Bonding was performed in a wafer bonder at 180 and 150degC for 20 min with a pressure of 5.5 MPa. It was found that bonding at 180degC voids free seal joints composed of high-temperature intermetallic compounds were obtained with good hermeticity. However, with bonding at 150degC, voids were generated along the seal joint, which caused poor hermeticity compared with that bonded at 180degC. After four types of reliability tests-pressure cooker test, high humidity storage, high-temperature storage, and temperature cycling test-dies bonded at 180degC showed good reliability properties evidenced by hermeticity test and shear tests. Results presented here prove that high-yield and low-temperature hermetic bonding using Sn/In/Cu metallization with thin Ti buffer layer can be achieved.

A hermetic chip to chip bonding at low temperature with Cu/In/Sn/Cu joint

A bonding joint between Cu metallization and evaporated Sn/In composite solder was produced at temperature lower than 200degC in air in this work. The isothermal solidification and subsequent interdiffusion of Cu and Sn/In took place along the bonding couples held at 180degC for 20 minutes. The interfacial reaction and the bonding quality is studied and evaluated. Scanning electron microscopy (SEM) exhibits the joint is uniform along the bonding interface and no crack or voids present, which has an interfacial tensile strength of 52 kg/cm2. The overall bonding is examined by C-mode scanning acoustic microscope (C-SAM). Fine leak rate test shows the leak rate is about 5.8x10-9 arm-cc/s which indicates a hermetic sealing. Intermetallic compounds (IMCs) such as Auln2, Cu6Sn5 and Cu11ln9 have been detected by means of X-ray diffraction analysis (XRD) and transmission electron microscopy (TEM) accompanied with energy dispersive X-ray (EDX). The chemical composition analysis also reveals that solder interlayers, Sn and In, have been completely converted into IMCs by reacting with Cu. All IMCs formed in the joints have re-melting temperature above 300degC according to Cu-In, Cu-Sn and Au-In phase diagrams. Therefore, the joint can sustain high service temperature due to the presence of IMCs. Such technique producing the joints with the good bond quality and high re-melting point has great potential in electronics and microelectronics packaging such as MEMS packaging and photonic packaging.