Fengwei Dai

The development of low cost Through Glass Via (TGV) interposer using additive method for via filling

Through Glass Via (TGV) is a new approch for Three-dimensional (3D) integration packaging. In this paper, a novel low cost process for manufacture TGV wafer was introduced. Different materials and process were compared. RF MEMS using TGV wafer was designed.

Accurate electrical simulation and design optimization for silicon interposer considering the MOS effect and eddy currents in the silicon substrate

In this paper, a group of coplanar lines on a silicon dioxide insulating layer on a nominally doped silicon substrate is simulated and measured. Electrical parameters extracted from published data are used and lead to substantially improved agreement with measurements. In addition, several models of redistribution layer (RDL) with different shape-TSVs (through silicon vias) are simulated, along with two different joint structures between TSV and RDL. Simulation result suggest that because the electrical length is very short reflection losses attributed to the structural details of the TSV may be ignored in the applicable frequency band of the TSV. In addition, several optimized transmission line structures are designed and simulated. Results suggest that design criteria used to optimize lines in organic substrates are not directly transferable to a silicon substrate. This paper shows a simple but effective method with which to analyze the influences exerted by the metal oxide semiconductor (MOS) capacitance at the TSV interface and eddy currents in the substrate on a transmission line. Finally, newly de-embedded test structures are provided to extract spice model parameters for TSV modeling.

Numerical simulation and experimental verification of copper plating with different additives for through silicon vias

The Filling of high aspect ratio through silicon vias (TSVs) using copper plating without any void or seam is one of the technical challenges for 3D integration. This paper presents numerical simulation and experimental verification of copper plating with different additives and a guideline for process optimization is proposed. Theoretical models are derived and a generic calculating approach is developed by employing a variable boundary method using commercial software. The simulation results can predict the behaviors of copper plating with different levels of additives for blind vias. The further experimental results verified the theoretical model and the simulation results. TSVs with diameter of 30μm and depth of 160μm on 8 inch wafers without void or seam have been achieved.

Spray coating process with polymer material for insulation in CIS-TSV wafer-level-packaging

This paper presents a novel spray coating process for the forming of sidewall insulation of through silicon via (TSV) which was a challenging process in CMOS image sensor (CIS) packaging. In conventional way, silicon oxide by plasma enhanced chemical vapor deposition (PECVD) is chosen as insulation material. In this paper, one kind of phenolic aldehyde polymer is deposited on the sidewall of though silicon via with the diameter of 75μm and depth of 100μm by novel spray coating process. To avoid the failure of TSV sidewall insulation and electrical interconnection characteristic, the thickness of polymer on the sidewall should be not less than 2μm. To achieve the insulation layer thickness target value, the temperature of spray coating process temperature was adjusted to control the viscosity of polymer. After the process optimization, the minimum thickness of sidewall polymer insulation layer is over 2.5μm meanwhile the conformal coverage characters of sidewall insulation layers are promoted.

Effect of IMC growth on thermal cycling reliability of micro solder bumps

In this study, thermal cycling reliability tests and analysis for micro solder bump in 2.5D packaging were conducted. Finite element analysis modeling of micro bump with different intermetallic compound (IMC) thickness was developed to model the effect of IMC layer on fatigue behavior of micro bumps. It was found that stress in solder increased notably when the IMC layer is taken into consideration, and increased slightly as further increase in the IMC thickness. The thermal mechanical stress in IMC layer was also studied to assess the reliability of IMC integration. It was found that the stress decreased sharply with the increase of IMC thickness; when all the solder transformed into IMC, the thermal mechanical stress decreased to only 20% of the stress in 1μm IMC. Failure mode after thermal cycling tests was analyzed by cross section morphology. Cohesive cracks in the solder took place at the interface of tin solder and IMC layer, and heavier damage was found in bumps with thicker IMC thickness, which agreed well with the FEA results.

Newly developed in-situ formation of SnAg and SnAgCu solder on copper pillar bump

The trend to smaller and lighter electronics has accentuated efforts towards high density, increased performance and miniaturization in packaging technology. Fine pitch micro bump interconnection can greatly improve the interconnect density, thereby becoming a mainstream technology of high-density packaging. A new method to fabricate binary and ternary solder bump based on electroplating and micro-alloying are introduced in present paper. The formation of SnAg and SnAgCu alloys on copper pillar bump is demonstrated. The new manufacturing process is explained as follows. Firstly, alloying metals such as Ag and Cu are deposited at the surface of the electroplated Sn layer over copper pillar by physics vapor deposition (PVD). Then, the multi-component solder bump is formed through a reflow process. By scanning electron microscope (SEM) and Energy Dispersive Spectrum (EDS) analysis, it was confirmed that Ag and Cu layers over Sn have dissolved into the solder and formed intermetallic compound (IMC) in the solder after first reflow. After 1000 temperature cycles up to −50∼85°C, Ag3Sn phase precipitation was observed having stick or island shapes. But we did not observe tin whisker on the surface of the solder bump.

Study of equivalent thermal modeling and simulation of 2.5D/3D stacked dies module

In the paper, an equivalent modeling method is proposed to simplify thermal simulation model of 2.5D stacked dies modules. A TSV and its surrounding silicon substrate or a micro bump and its surrounding underfill will be equivalent to a single body of material. Through this method, we will not only be able to obtain thermal characteristics of each part of the stacked dies module, but also can greatly simplify the calculation amount of numerical simulation. According to this method, we obtained thermal distribution map of 2.5D/3D stacked dies module; in addition, to guide and optimize thermal management design, we analyzed the influence of several parameters on maximum junction temperature of 2.5D stacked dies as well, such as spacing among dies, thermal conductivity of TIM2 (Thermal Interface Material), ambient temperature, wind speed and so on. It was found that with the increase in spacing among dies, the maximum junction temperature of dies decreases and the maximum decreasing amplitude is 4.4°C. Secondly, impact on the maximum junction temperature of die, the ambient temperature of the cabinet is the most serious. Finally, the wind speed of the cabinet and the thermal conductivity of TIM2 (Thermal Interface Material) also have a great effect on the maximum junction temperature of die.

Three-dimensional PN junction capacitor for passive integration

A wafer level three-dimensional (3D) PN junction capacitor for passive device integration on Si is developed. The 3D capacitor structure is created by deep trench etching of Si and appropriate doping. The salient characteristics of the PN junction capacitors fabricated in this study are as follows. The maximum areal capacitance density is 11.5 fF/μm2, the highest breakdown voltage is −20 V, and the minimum leakage current is 5 nA at an applied reverse voltage of −5 V. In comparison with the planar PN junction capacitor, the 3D junction capacitor can provide 8-12 times the capacitance density at the same doping concentration.

A study of high-density embedded capacitor for silicon-substrate package

Rapidly growing performance and mixed-signal integration is driving the need for product component miniaturization in electronics applications. Embedded passive technology is a potentially attractive solution to replace discrete passives. Embedded capacitors are widely used for broad range of applications including filtering, tuning and power-bus decoupling in the substrate. Micro-Electron-Mechanical System (MEMS) process based on silicon and deep etching 3D patterns on silicon substrate is used. The fabrication process and properties of a semiconductor decoupling capacitor with high capacitance density is reported in this paper. Measurement results indicate that the capacitance density can reach 12nF/mm2, which is 10–12 times that planar semiconductor capacitors, and that the decoupling frequency range is between from 10MHz to 3.2GHz.

The study of backside TSV reveal process by direct Si/Cu grinding and polishing

Despite the fact that manufacturing processes of through silicon via (TSV) have achieved great progresses, the backside via reveal process is still challenging and costly. The simplest TSV reveal method is using backside grinding (BG) and chemical mechanical polishing (CMP), by which the vias are revealed by CMP directly after wafer thinning with BG. However this method is not well accepted due to the Cu contamination concern. From the application point of view, if the Cu contamination is restrained in pretty low level with process optimization, it may be still possible to be applied to achieve the simple and economical process, especially for 2.5D interposer manufacturing which is more tolerant with Cu contamination. In this work, very low contamination level-copper atoms (lower than 0.000001%) were got in backside wafer surface after CMP of TSV vias, which is good enough for interposer or even 3DIC application.