Chongshen Song

Effect of thermal annealing on TSV Cu protrusion and local stress

Through silicon vias (TSVs) are regarded as one of the key enabling component to achieve three-dimensional (3D) integrated circuit (IC) functionality. In this paper, we present the investigation on TSV protrusion and stress at different annealing conditions tested by means of optical profiler and high efficiency micro-Raman microscopy. Finite element method is utilized to model and simulate the thermo-mechanical behavior of the TSV having a diameter of 20 μm and a depth of 120 μm under different annealing temperatures. The measured protrusion increases with annealing temperature below 400°C, and then decreases when being further annealed. The maximum measured silicon stress as a function of annealing temperature has shown similar trend to the protrusion. The pre-annealing has limited effect on protrusion, but is helpful to reduce the silicon stress.

Accurate electrical simulation and design optimization for silicon interposer considering the MOS effect and eddy currents in the silicon substrate

In this paper, a group of coplanar lines on a silicon dioxide insulating layer on a nominally doped silicon substrate is simulated and measured. Electrical parameters extracted from published data are used and lead to substantially improved agreement with measurements. In addition, several models of redistribution layer (RDL) with different shape-TSVs (through silicon vias) are simulated, along with two different joint structures between TSV and RDL. Simulation result suggest that because the electrical length is very short reflection losses attributed to the structural details of the TSV may be ignored in the applicable frequency band of the TSV. In addition, several optimized transmission line structures are designed and simulated. Results suggest that design criteria used to optimize lines in organic substrates are not directly transferable to a silicon substrate. This paper shows a simple but effective method with which to analyze the influences exerted by the metal oxide semiconductor (MOS) capacitance at the TSV interface and eddy currents in the substrate on a transmission line. Finally, newly de-embedded test structures are provided to extract spice model parameters for TSV modeling.

Numerical simulation and experimental verification of copper plating with different additives for through silicon vias

The Filling of high aspect ratio through silicon vias (TSVs) using copper plating without any void or seam is one of the technical challenges for 3D integration. This paper presents numerical simulation and experimental verification of copper plating with different additives and a guideline for process optimization is proposed. Theoretical models are derived and a generic calculating approach is developed by employing a variable boundary method using commercial software. The simulation results can predict the behaviors of copper plating with different levels of additives for blind vias. The further experimental results verified the theoretical model and the simulation results. TSVs with diameter of 30μm and depth of 160μm on 8 inch wafers without void or seam have been achieved.

Study of equivalent thermal modeling and simulation of 2.5D/3D stacked dies module

In the paper, an equivalent modeling method is proposed to simplify thermal simulation model of 2.5D stacked dies modules. A TSV and its surrounding silicon substrate or a micro bump and its surrounding underfill will be equivalent to a single body of material. Through this method, we will not only be able to obtain thermal characteristics of each part of the stacked dies module, but also can greatly simplify the calculation amount of numerical simulation. According to this method, we obtained thermal distribution map of 2.5D/3D stacked dies module; in addition, to guide and optimize thermal management design, we analyzed the influence of several parameters on maximum junction temperature of 2.5D stacked dies as well, such as spacing among dies, thermal conductivity of TIM2 (Thermal Interface Material), ambient temperature, wind speed and so on. It was found that with the increase in spacing among dies, the maximum junction temperature of dies decreases and the maximum decreasing amplitude is 4.4°C. Secondly, impact on the maximum junction temperature of die, the ambient temperature of the cabinet is the most serious. Finally, the wind speed of the cabinet and the thermal conductivity of TIM2 (Thermal Interface Material) also have a great effect on the maximum junction temperature of die.

Nonlinear thermal stress & strain analysis of through silicon vias with different structures and polymer filling

Due to the differences in the thermal expansion coefficients of copper and silicon, a large thermal stress develops at the interface between a Cu-filled via and both the insulation layer and the surrounding silicon when the structure is subjected to temperature loading. In this paper four TSV geometries are considered in an effort to investigate the role of via geometry on stress relief. Thermo-mechanical finite element method (FEM) simulation software is used to analyze the influence of TSV shape on the nonlinear thermal stresses and strains generated under temperature cycling. The height (H) and radius (D) of a via are varied in the simulations in order to evaluate the magnitude and distribution of the thermal stress. In addition, various insulation materials and thicknesses are also considered in order to evaluate their thermo-mechanical behaviors. Thermal stress decreases with increasing SiO2 insulator thickness up to the process maximum of 1 um. In the case of Parylene, when the insulator thickness is less than 5 um, the stress value decreases to minimum for a polymer thickness of 5 um, thereafter increases showing an optimal thickness for minimum thermal stress. Finally, the vias with polymer filling are simulated.

Robust and Low Cost TSV Backside Reveal for 2.5D Multi-Die Integration

TSV backside reveal is one of the key process modules for enabling 2.5D integration. This paper presents a robust and low cost solution for TSV backside reveal. 300mm wafers with a TSV size of 10μm×100μm are used to evaluate the proposed backside reveal solution. A high selective wet etching process with an etch rate of about 15 μm/min is used to replace conventional Si dry etching step for Si recess etch. A low temperature cured polyimide layer is used for the backside passivation and an innovative exposure treatment is employed to expose the back tip of the TSVs. After silicon oxide dry etching, the TSV metal is revealed for backside interconnection. This process can avoid Si dry etching, plasma deposition and chemical mechanical polishing (CMP) processes and hence the overall cost is significantly reduced. Furthermore, the process margin for TTV control is also relaxed, which leads to a robust process result. Electrical test results for TSV kelvin and TSV daisy chain show a high process yield and a low contact resistance between the TSV back tip and backside RDL layer. Finally, 2.5D multi-die integration is demonstrated based on the proposed process.

Development and thermo-mechanical stress analysis of TSVs filling with Sn-based intermetallics

With the trend of commercialization of through-silicon vias (TSVs) in 3D integrated microsystems, new TSVs filling processes are developed to meet the requirement of low-cost fabricating of high-electrical performance and high-thermal reliability TSVs without any voids. In this paper, Sn-based IMCs are used as the filling materials for the formation of conductive path of TSVs. The Sn-based IMCs filling process is studied and the initial results are reported. Thermal-mechanical stress analysis of TSVs with different filling materials is performed through finite element analysis (FEA). The isotropic and anisotropic elastic property of silicon is considered in the FEA modeling. A static temperature ramp down analysis from 125°C to -40°C was carried out to simulate the maximum thermal stress state. The simulation results indicate that the TSVs filled with Cu6Sn5 and Ni3Sn4 exhibit lower thermal stress compared with solder TSVs and even Cu TSVs.

Comprehensive analysis of thermal mechanical stress induced by Cu TSV and its impact on device performance

3D integration using TSVs is a promising method to achieve further improvements for future electronic systems. When Copper TSVs are fabricated, Stress is induced in silicon near the TSV by CTE mismatch between filling copper and silicon substrate. For the substrate which has active circuits, the induced stress will influence the performance of the devices fabricated therein. To understand the impact of TSV induced stress on device performance deeply, this paper gives a comprehensive study. Orthotropic feature of silicon is considered to calculate the stress profile in silicon in vicinity of the Cu TSV. The saturation drain current variation of MOSFETs is calculated from the simulated stress data using the theory of piezoelectric effect. The results can well match the reported measuring data and show that it is an effective method to deeply understand the TSV induced stress and its impact on device performance.

Development of new TSV structure composing of intermetallic compounds

TSV was regarded as the core technology enabling 3D IC integration. For volume production, the requirement of low-cost TSV fabrication process was a big challenge. In order to find a fast filling method, new Cu plating solutions are desirable and some new filling method using solder, Cu cored solder ball were studied. A new TSV structure composed of intermetallic compounds (IMCs) was proposed in present paper and the manufacturing process was introduced. To form such a TSV structure, it needs to fill liquid solder into the vias and accelerate the inter-diffusion of solder and metal on the sidewall of the vias by annealing. The feasibility of the formation of IMC TSVs was studied using SnPb solder. The solder was filled into the vias in which partial annular Cu layer was plated. Successful voids free filling with thin protrusion of solder material on the top of the vias was achieved. Finite element analysis (FEA) of TSV filling with Cu, solder and Sn-based IMC were carried out and the results showed that the IMC filled TSVs can get comparable or even lower stress depending on the CTE of the IMCs. According to present results, it can be concluded that the IMC TSVs have the following merits: fast and low cost forming process, good high temperature stability and the lower stress.

Development of micro-alloying method for Cu pillar solder bump by solid liquid interaction

Fine pitch micro bump is one of the key technology for 3D packaging since it can greatly improve the interconnect density. In this paper, we describe a new micro-alloy method for joining Cu pillars by forming solder bump alloys. The alloy composition is controlled by thin metal layer deposition and subsequent solid-liquid interactions. Four elements, e. g., Ag, Cu, Ni and Cr, were selected for micro-alloying Cu/Sn bumps and compositions of Sn-(1~2)Ag, Sn-2Ag-0.5Cu, Sn-(0.03~0.07)Ni, and Sn-(0.03~0.07)Cr were formed on Cu pillars. The microstructure of the solder bumps was studied before and after temperature cycling. The alloying process, and the effect of alloying on the interfacial microstructure and the growth of the intermetallic compounds (IMC) were investigated. The results suggest that the dissolution rate of additional metal in the molten Sn is sufficiently rapid to form solder bumps of varying compositions during a single reflow step. With Ag alloying, Ag3Sn crystals formed and were finely dispersed in the solder. With trace Ni doping, Ni was dissolved into the solder and the IMC layer thickness increases since the Cu solubility in molten Sn increases in the presence of Ni. In comparison, it is quite interesting that with trace Cr alloying, Cr2Sn3 crystals were detected in the solder and that a thinner IMC layer resulted in comparison to Ni-alloying solder and pure Sn on Cu pillars. The susceptibility to whisker growth during alloying was also investigated. No Sn whisker formation or growth was observed on the solder bumps after 1000 thermal cycles. The thickness of IMC layer became thicker after temperature cycling. In decreasing order, the thickness of the IMC layer on the Cu pillar was observed to be: Sn-0.07Ni>;Sn-2Ag>;Sn-0.07Cr>;Sn-2Ag-0.5Cu.