Marc A. Mangrum

Non-contact Testing for SoC and RCP (SIPs) at Advanced Nodes

Non-contact methods for testing system-on-chip (SoC) and system in package (SIP) assemblies are presented. This method allows for high speed testing at the wafer level for SoCs as well as testing during and after assembly for panel or wafer level SIP technologies. Wafer testing at advanced nodes is carried out without damaging underlying metallurgy - an issue with current contact testing techniques. The technology utilizes non-contact GHz short-range transceivers to transfer test signals and results to and from SoC ICs. The wireless probes convert standard tester ATE logic levels to high frequency RF (GHz) transceiver signals and thus allow the use of standard test equipment. A reduced set of contact probes are used for test power only. A 45 nm fully CMOS compatible IC with wireless test transceivers is designed and fabricated. Enhancing the reliability and economics of IC manufacture by enabling non-contact testing of SoCs before and during packaging is a key benefit of this technology.

Implementation of a mobile phone module with redistributed chip packaging

The redistributed chip packaging is an embedded chip technology that eliminates the need for wirebonds and flip chip bumps. This technology enables smaller packages at a lower cost, while providing improved mechanical, electrical and thermal performance. The process involves producing panels placing the chip active face down along with an embedded ground plane (EGP) and screen printing encapsulant to embed the die. Subsequently alternate layers of dielectric and Cu metallization are built up and the packages are sawn into individual units. The use of wafer fabrication tools enables finer lines and spaces in the build-up layers. This paper will discuss process conditions during the panelization and the integration of the base function of an i.275 GSM/EDGE mobile phone into a single module measuring a maximum of 1 square inch. The design of the EGP and the role of simulations to achieve a robust, reliable package will also be discussed. The outputs included moisture sensitivity level (MSL) 3 testing, air-to-air thermal cycling (- 40C/125C) and unbiased highly accelerated stress testing (HAST). Testing of RCP packages will also be discussed.

Packaging technologies for mobile platforms

As electronic devices do more in less space, the technologies that enable them are challenged to do the same. Semiconductor packaging is no exception. As manufacturers attempt to integrate more functionality into slimmer, smaller form factors, advanced packaging, along with SOC integration, is used to reduce the size, cost and power consumption of the integrated circuits inside those mobile devices. New technologies such as multi-die SiP (system-in-package), stacked packages or PoP (package-on-package), packages integrating other packages or PiP (package-in-package), packages that integrate passives with silicon die or LTCC (low temperature co-fired ceramic) and finally redistributive chip packaging (RCP), all promise to improve performance and reduce package sizes. These innovations in IC packaging technology will enable manufacturers of converged products such as smart phones and multimedia players, to create the small, sleek multifunction devices to meet their market demands. However, each of these packaging technologies has trade-offs and benefits that should be carefully evaluated prior to final selection a device packaging solution.