Lakshmi N. Ramanathan

Spalling of Cu3Sn intermetallics in high-lead 95Pb5Sn solder bumps on Cu under bump metallization during solid-state annealing

We report the spalling of Cu3Sn intermetallics in high-lead 95Pb5Sn solder bumps on Cu under bump metallization (UBM) during solid state annealing. Upon reflow, the Cu3Sn intermetallics formed on Cu UBM. However, after solid state annealing at 170 °C, the Cu3Sn intermetallics spalled off from Cu UBM and the Pb phase filled the gap between the Cu3Sn intermetallics and Cu UBM. This is primarily explained by the loss of chemical adhesion between the Cu3Sn intermetallics and Cu UBM due to no additional chemical reaction. Thermodynamic principles are used to interpret the spalling phenomenon and the analysis showed that the interfacial free energy without spalling is greater than that with spalling after solid-state annealing. Spalling of the Cu3Sn intermetallics initiated at an open interface such as the edge of Cu UBM and finally extended to the flat interface at a slower rate.

Electromigration statistics and damage evolution for Pb-free solder joints with Cu and Ni UBM in plastic flip-chip packages

A series of electromigration (EM) tests were performed as a function of temperature and current density to investigate lifetime statistics and damage evolution for Pb-free solder joints with Cu and Ni under-bump-metallizations (UBMs). The EM lifetime was found to depend on the failure criterion used, so the results were compared based on the first resistance jump and conventional open-failure criterion. Solder joints with Cu UBM had a longer lifetime than Ni UBM based on the open-failure criterion, but the lifetime with Ni UBM became comparable when the first resistance jump criterion was applied. To determine the temperature in solder joints, the Joule heating effect was investigated with experiments and finite element analysis. The temperature of solder joints was determined to be approximately 15°C higher than that at the Si die surface when 1 A of current was applied. With the appropriate temperature correction, the activation energies and the current density exponents were found to be Q = 1.11 eV, n = 3.75 and Q = 0.86 eV, n = 2.1 based on the open-failure criterion for solder joints with Cu and Ni UBM, respectively. Based on the first resistance jump criterion, Q = 1.05 eV, n = 1.45 for Cu UBM and Q = 0.94 eV, n = 2.2 for Ni UBM, respectively. For solder joints with Cu UBM, voids were formed initially at the Cu6Sn5/solder interface while the final open failure occurred at the Cu3Sn/Cu6Sn5 interface. For Ni UBM, voids were formed initially at the Ni3Sn4/solder interface leading to failure at the same interface. The formation of intermetallic compounds (IMCs) was enhanced under current stressing, which followed linear growth kinetics with time. The IMC growth was accompanied by volume shrinkage, which accelerated damage evolution under EM.

Electromigration lifetime statistics for Pb-free solder joints with Cu and Ni UBM in plastic flip-chip packages

A series of electromigration tests were performed as a function of temperature and current density to investigate lifetime statistics for Pb-free solder with Cu or Ni under-bump-metallization (UBM). Based on the overall shape of resistance traces, a conservative failure criterion for time-to-failure was defined and the results were compared with those based on the conventional open-failure criterion. Solder joints with Cu UBM had a longer lifetime than with Ni UBM, based on the open-failure criterion; however, the lifetime with Ni UBM became comparable when the conservative criterion was applied. The Joule heating effect was accounted for based on experiments and finite element analysis. The temperature of solder joints was determined to be approximately 15degC higher than that at the Si die surface when 1 A of current was passed. For solder with Cu UBM, voids formed initially at the Cu6Sn 5/solder interface while the final open failure occurred at the Cu3Sn/Cu6Sn5 interface. For Ni UBM, voids formed initially at the Ni3Sn4/solder interface leading to failure at the Ni3Sn4/solder interface

Electromigration behavior of lead-free solder flip chip bumps on NiP/Cu metallization

The electromigration behavior of Sn–2.5Ag and Sn–0.7Cu (in wt %) flip chip solder joints on electroless NiP/Cu metallization at a current density of 1.3×104 A/cm2 was studied. For Sn-2.5 Ag solder, electromigration at 115 °C for 250 h showed a selective dissolution of Ni from the electroless NiP layer forming crystallized Ni3P. At 140 °C, the damage to the NiP layer was accelerated and instability of the NiP/Cu interface was observed. For eutectic Sn–0.7Cu solder, the electromigration behavior at a higher temperature was evaluated. At 180 °C, the NiP/Cu under bump metallurgy (UBM) started to show damage after 50 h. At 200 °C, the entire NiP/Cu layer was damaged, and P in the NiP layer moved to the edge of the anode much faster than the other species forming CuP2 intermetallics. NiP/Cu UBM experiences selective dissolution of Ni at lower temperatures, and the damage of the entire UBM occurred abruptly at the higher temperature.

Emerging reliability challenges in electronic packaging

The trend for microelectronic devices has historically been, and will continue to be, towards smaller feature size, faster speeds, more complexity, higher power and lower cost. The motivating force behind these advances has traditionally been microprocessors. With the tremendous growth of wireless telecommunication, RF applications are beginning to drive many areas of microelectronics traditionally led by the development of the microprocessor. An increasingly dominant factor in RF microelectronics is electronic packaging and the reliability of the package and the materials that comprise the package and, in particular, the solder interconnects. The need for Pb-free assembly and the application to hand-held electronics has challenged the reliability of electronic packages. This paper discusses packaging reliability of solder interconnects for hand-held wireless and RF applications and describe the tests used to evaluate reliability. The specific reliability issues discussed will be thermomechanical stress (fatigue), solder joint electromigration (DC and RF) and high speed impact stresses (drop test performance).

Implementation of a mobile phone module with redistributed chip packaging

The redistributed chip packaging is an embedded chip technology that eliminates the need for wirebonds and flip chip bumps. This technology enables smaller packages at a lower cost, while providing improved mechanical, electrical and thermal performance. The process involves producing panels placing the chip active face down along with an embedded ground plane (EGP) and screen printing encapsulant to embed the die. Subsequently alternate layers of dielectric and Cu metallization are built up and the packages are sawn into individual units. The use of wafer fabrication tools enables finer lines and spaces in the build-up layers. This paper will discuss process conditions during the panelization and the integration of the base function of an i.275 GSM/EDGE mobile phone into a single module measuring a maximum of 1 square inch. The design of the EGP and the role of simulations to achieve a robust, reliable package will also be discussed. The outputs included moisture sensitivity level (MSL) 3 testing, air-to-air thermal cycling (- 40C/125C) and unbiased highly accelerated stress testing (HAST). Testing of RCP packages will also be discussed.

Current Carrying Capability of Sn0.7Cu Solder Bumps in Flip Chip Modules for High Power Applications

The primary objective of this work was to characterize the current carrying capability of Sn0.7Cu solder bumps for use in high power flip chip module applications. The factors to be considered in using modules as test vehicles for current carrying capability studies are explored. Experimental data on the current carrying capability of Sn0.7Cu solder bumps in a module test vehicle is complemented with thermal simulations to understand the phenomena occurring the first level solder interconnects. The associated electromigration characteristics of the Sn0.7Cu on plated Cu was also evaluated. Current densities of 6.0x103, 9.42x103, 1.06x104, and 1.18x104 A/cm2 were investigated at 115C, 125C and 135C. No failures were observed for up to 2550 hours with the lowest current level of 6.0x103 A/cm2 at 135C. However, a variety of failure modes were seen at the other current levels. In this work a thermocouple was used to approximate the temperature of the solder bump. While this method has produced excellent results in obtaining the electromigration of solder bumps in single die applications, failure analysis and thermal simulation indicated that this is not the case with flip chip modules. A Computational Fluid Dynamics (CFD) tool was employed and thermal modeling confirmed that the bump temperature was significantly higher than the temperature measured on the surface of the mold compound. Temperature gradients played a significant role in determining the electromigration characteristics and extra considerations are needed to examine the multiple effects resulting from it.

Engineering nano interfacial layers for low contact resistance in chip to package interconnects

This paper presents a study on the contact resistance of interconnects between chip and package of embedded chip technology. Multi-layered aluminum/titanium tungsten/copper interconnects (Al/TiW/Cu) were used as the model system. Design of experiment was carried out to characterize the effect of under bump metallurgy deposition steps, including the degas and radio frequency (RF) plasma etch steps, on contact resistance. A minimum level of degassing is needed, but the resistance was significantly affected by the amount of RF etch. Extensive failure analysis was done using focus ion beam (FIB), Auger electron spectroscopy (AES), scanning electron microscope (SEM), high resolution transmission electron microscope (HRTEM), and secondary ion mass spectroscopy (SIMS) to correlate the resistance to the quality of the bond pad surface and its interface with overlying TiW/Cu under bump metallurgy layers. With a carefully engineered solution, the contact resistance of aluminum/titanium tungsten/copper interconnects between chip and package was reduced almost 3 orders of magnitude to 10 milliohm range. FIB, SEM, AES, HRTEM, and SIMS were used to characterize the nano interfacial layers of both high contact resistance and low contact resistance samples. HRTEM showed the presence of a distinct interfacial layer between TiW and Al interface for both high and low resistance samples, which has not been reported before. The thickness and composition were characterized using SIMS and HRTEM. The macroscopic resistance characteristics were correlated to the state of the interface as established by SIMS and HRTEM.

Electromigration behavior of flip-chip solder bumps subjected to RF stressing

A test system was built to evaluate RF electromigration characteristics of solder interconnections. The test system measured DC resistance and RF insertion loss and testing was done with high frequency RF signals superimposed on 0 A, 0.25 A or 0.5 A of DC current at elevated temperatures. The test vehicle consisted of daisy chain test Si die with Sn0.7Cu flip chip bumps on 11 mum of plated Cu/Cu/TiW UBM and GaAs die with Sn2.5Ag flip chip bumps on 2 mum plated Ni/Ti UBM. RF stressing resulted in brittle intermetallic structures on the surface of the solder bumps, which is not seen with pure DC stressing. Furthermore, the RF energy created damage through electromagnetic induction current on neighboring unstressed bumps. The superimposition of a 0.5 A DC current on the RF signal accelerated the bump damage rate. In this paper a description of the daisy chain test vehicle, factors considered in RF electromigration testing, variation of DC resistance and RF insertion loss with time, failure analysis using cross-sections and SEM will be used to explain the effect of RF stressing on solder bump behavior.