Darrell M. Erb

Calculation of effective dielectric constants for advanced interconnect structures with low-k dielectrics

Effective dielectric constants of advanced interconnects with low-k and ultra-low-k dielectrics were evaluated by two-dimensional capacitance analysis. The analysis was performed for interconnect design rules proposed for 65 nm node high-performance integration. Interconnects with various pitches and integration schemes were examined, and the effects of supporting dielectric layers including cap layer, chemical mechanical polishing stop layer, and etch stop layer were evaluated. The results indicated that the use of the supporting layers greatly affects the effective dielectric constant of interconnect structures. The impacts of the supporting dielectric layers on the effective dielectric constant were evaluated quantitatively, and the implications on back-end-of-line integration schemes were discussed.

A double-epitaxial process for high-density DRAM trench-capacitor isolation

A new double-epi structure for isolating deep (>5 µm) trench capacitors with 1 µm or less spacing is described. This technique consists of a thin lightly doped upper epilayer on top of a thicker and more heavily doped bottom layer of epi. The low resistivity bottom epilayer is designed to isolate trench capacitors of any depth. The upper layer with high resistivity is used for the CMOS periphery and can be selectively doped to achieve a near-uniform concentration to isolate trench capacitors in the core. Isolation between deep trenches at 1.0-µm spacing has been demonstrated to be applicable for 4 Mbit and greater DRAM integration levels.