Christy Mei-Chu Woo

Replacement metal-gate NMOSFETs with ALD TaN/EP-Cu, PVD Ta, and PVD TaN electrode

This work reports the first replacement (damascene) metal gate NMOSFETs with atomic layer deposition (ALD) TaN/PVD and electroplated Cu as the stacked gate electrode. Transistors with PVD TaN and PVD Ta electrode are also fabricated. Our data show that ALD TaN has the right work function for the N-MOSFETs. The Cu damascene process can reduce the gate resistivity. The ALD process has the advantage of reducing the stress and radiation damage to the gate oxide. The damascene process flow bypasses high temperature steps (>600/spl deg/C)-critical for metal gate and high-k materials.

A low-temperature metal-doping technique for engineering the gate electrode of replacement metal gate CMOS transistors

This work describes a low-temperature metal annealing technique that can be a helpful tool for fabricating the gate electrode of replacement metal gate CMOS transistors. The goal of the technique is to form doped metal (TaSiN, TiSiN, TaCN, TaPN, etc.) to change the work function of the metal gate electrode. The low-temperature doping process was performed in an ambient containing the precursors of the dopants, including silane, phosphine, and carbon-rich organic precursors. Experiments have been conducted to incorporate dopants such as P, C, Si into TaN or TiN. The transistor and C-V data show the resultant doped metals are suitable materials for P- and N-MOSFETs by providing the right metal work function.

Deep sub-100 nm CMOS with ultra low gate sheet resistance by NiSi

CMOS devices down to 50 nm gate length were fabricated with NiSi salicide for the first time. Edge effects of Ni-polycide formation, enhanced by a recessed spacer, results in gate Rs roll-off with poly line width. Ultra low /spl sim/2 /spl Omega///spl square/ gate Rs is achieved for 50 nm line width with low junction leakage. Source/drain series resistance is significantly reduced and, consequently, drive current is improved with NiSi. Ring oscillator speed measurements showed significant improvement in gate delay with NiSi, especially for the ring oscillators made with large gate width devices.

The effect of annealing temperatures on self-aligned replacement (damascene) TaCN-TaN-stacked gate pMOSFETs

In this paper, we report the first self-aligned replacement (Damascene) TaCN-TaN-stacked gate electrode pMOSFETs. The high-temperature (>1000/spl deg/C) implant activation anneal was done prior to the metal electrode deposition. After the fabrication was completed, the transistors were then annealed at lower temperatures (300/spl deg/C-600/spl deg/C), which might affect the critical device parameters, such as subthreshold slope, threshold voltage, gate leakage, on, and off currents. Our data show that TaCN is a promising material for the metal-gate pMOSFETs due to the suitable metal work function and good thermal stability up to 500/spl deg/C, which is much higher than the highest temperature required by the backend very large-scale integration process.

Measuring The Work Functions Of PVD TaN, TaSiN And TiSiN Films With A Schottky Diode CV Technique For Metal Gate CMOS Applications

The metal gate process becomes a promising candidate for sub-65nm CMOS, due to the elimination of polysilicon depletion effects, and the possibility of adjusting the CMOS threshold voltage without more threshold implants. Our goal is to process mteal films with tunable work functions, in order to meet the demand of sub-65nm metal gate CMOS. PVD TaN films are deposited with various processing conditions. Auger analysis shows that by changing the nitrogen flow rate and the plasma power, the nitrogen content in the TaN films can be adjusted. In order to accurately determine the work function of these TaN materials, we have developed a Schottky Diode CV technique (or Metal-Silicon CV, or MS-CV). This approach not only improves the accuracy of the metal work function measurement, compared with the traditional MOS-CV technique (which is affected by the thickness and quality of the oxide), but also simplifies the fabrication. With the MS-CVs, we have successfully measured the work functions of Ni and Co, and compared the data with published references. The work function of PVD TaN actually decreases with higher nitrogen content, according to the Auger data and the MS-CV measurement, ranging from 3.42 – 4.20 Volts. The MS-CV technique is shown to be independent to the size of the capacitors, and is little affected by the measurement frequency. By changing the frequency from 100KHz to 1MHz, the error in the work function is less than 50mV.

Self-aligned nickel, cobalt/tantalum nitride stacked-gate pMOSFETs fabricated with a low temperature process after metal electrode deposition

This letter reports the first replacement (Damascene) metal gate pMOSFETs fabricated with Ni/TaN, Co/TaN stacked electrode, where Ni or Co is in direct contact with the gate SiO/sub 2/, to adjust the electrode metal work function and TaN is used as the filling material for the gate electrode to avoid wet etching and CMP problems. The process is similar to the fabrication of traditional self-aligned polysilicon gate MOSFETs, except that in the back end (after the source/drain implants are activated) a few processing steps are added to replace the polysilicon with metal. Our data show that the Ni or Co/TaN gate electrode has the right work function for the pMOSFETs. The metal gate process can reduce the gate resistivity. Thermal stability of the stacked electrodes is studied and the result is reported in this paper. The damascene process flow bypasses high temperature steps (> 400/spl deg/C)critical for metal gate and hi k materials. This paper demonstrates that a low temperature anneal (300/spl deg/C) can improve the device performance. In this paper, the gate dielectrics is SiO/sub 2/.