Amit P. Marathe

Nickel silicide metal gate FDSOI devices with improved gate oxide leakage

Fully depleted SOI (FDSOI) devices with undoped channel require metal gates to achieve correct threshold voltages. We demonstrate metal gate FDSOI devices using NiSi gates with symmetric V/sub t/ for both NMOS and PMOS devices. Metal gates are stable on 2 nm gate oxide and show capacitance equivalent gate oxide thickness (CET) 0.6 nm thinner than poly gates. The gate leakage current is up to two orders of magnitude lower and high mobility is achieved (peak electron mobility 670 cm/sup 2//Vs and 170 cm/sup 2//Vs for holes).

The effect of interlevel dielectric on the critical tensile stress to void nucleation for the reliability of Cu interconnects

We have conducted electromigration experiments and modeling on Cu Damascene structures surrounded by different interlevel dielectric ILD and Cu-cap materials. We have determined the mechanical properties of the surrounding ILD and Cu cap to play a key role in the critical stress change to void nucleation (Δσcrit), which is one of the critical parameters in determining electromigration lifetime or any other void-limited lifetime. Specifically, we found that Δσcrit decreases as the Young’s modulus of the interlevel dielectric decreases, which is the case with low-k materials. In order to compensate for the lower threshold to void nucleation in low-k materials, a stronger emphasis needs to be placed on the quality or adhesion of the Cu∕cap interface, which is currently the preferred site for void nucleation, so that interconnects fabricated in low-k materials continue to meet the ever-increasing electromigration reliability requirements. Finally, the methodology developed in this study, which is based on exp...

Simulation and experiments of stress migration for Cu/low-k BEoL

Stress migration (SM) or stress-induced voiding experiments were conducted for two back-end-of-line (BEoL) technologies: Cu/FTEOS and Cu/low-k. Experiments have shown the mean time to failure (MTF) depends on inter-layer dielectric (ILD) materials properties, ILD stack and metal line width. Stress migration is worse in Cu/low-k, manifesting as significantly reduced MTF under accelerated testing. Line width also has a more profound effect on stress migration reliability in Cu/low-k than in Cu/FTEOS. Wider lines produce higher failure rates, due to larger stress magnitudes in Cu and larger active diffusion volumes. Stress modeling using finite element analysis (FEA) was performed to quantify the stress fields in the via-chain test structure used for SM reliability testing. In order to account for the effect of process steps on stress evolution, a process-oriented modeling approach was developed. Stress in the metal line is a function of ILD properties, ILD stack and metal line width. The concept of an SM risk index is proposed to assess BEoL stress migration reliability from both stress and energy perspectives. Comparison of the SM risk index for Cu/FTEOS and Cu/low-k shows that the latter is more prone to stress-induced voiding. Stress migration tests verify that MTF values decrease with increasing line width. Modeling results are consistent with experimental findings, while providing more insightful understanding of stress-driven mechanisms in stress migration.

Electromigration-induced extrusion failures in Cu/low-k interconnects

Electromigration experiments were conducted to investigate the thresholds required for electromigration-induced extrusion failures in Cu/low-k interconnect structures. Extrusions at the anode were observed after long periods of void growth. Characterization of failure sites was carried out using scanning and transmission electron microscopy, which showed that failures occurred through delamination at the interface between the silicon-nitride-based capping layer diffusion barrier and the underlying Cu, Ta liner, and interlevel dielectric (ILD) materials. This interface is subjected to near tensile (mode I) loading with a mode mixity angle between 4° and 7°, estimated using finite-element-method analysis, as electromigration leads to a compressive stress in the underlying Cu. Comparisons of the fracture toughness for interfaces between the capping layer and individual underlayer materials indicate that the extrusion process initially involves plane-strain crack propagation. As Cu continues to extrude, the c...

The effect of low-k ILD on the electromigration reliability of Cu interconnects with different line lengths

We have compared the electromigration performance of Cu electromigration structures with varying line lengths imbedded in two different ILD materials. In the regime of high jL where there is no significant back-stress, we observed that three of the key electromigration parameters (i.e., MTF, n, and /spl sigma/) are constant and approximately equivalent between the two materials. In the regime of lower jL where there is significant back-stress, both materials exhibit similar trends, however, the Cu with low-k material performed relatively worse in terms of MTF and similarly in terms of n and /spl sigma/. That is, while the MTF of Cu with both materials increased with decreasing jL, the MTF of Cu with low-k material was less than that of the Cu with SiO/sub 2/-based material due to lower back-stress at a given jL. Further, while a regime of complete immortality was observed for the SiO/sub 2/-based material, no regime of immortality was observed for the low-k material. The values of n and /spl sigma/ were comparable for both materials, and were constant in the absence of significant back-stress but increased in the presence of significant back-stress. Due to the higher MTFs in the regime of high backstress, MTF is more sensitive to j and L, thereby increasing n as per Blacks Law. The increase in /spl sigma/ is a consequence of heightened sensitivity to process variations such as via barrier integrity and CD variation.

Stress modeling of Cu/low-k BEoL - application to stress migration

Stress migration (SM) or stress-induced voiding (SIV) experiments were conducted for two BEoL (Back End of Line) technologies: Cu/FTEOS and Cu/Low-k. Experiments have shown the mean time to failure (MTF) depends on ILD (interlayer dielectric) materials properties, ILD stack and metal line width. Stress migration is worse in Cu/low-k, manifesting as significantly reduced MTF under accelerated testing. Line width also has a more profound effect on stress migration reliability in Cu/low-k than in Cu/FTEOS. Wider lines produce higher failure rates, due to larger stress magnitudes in Cu and larger active diffusion volumes. Stress modeling using Finite Element Analysis (FEA) was performed to quantify the stress fields in the via-chain test structure used for SM reliability testing. In order to account for the effect of process steps on stress evolution, a process-oriented modeling approach was developed. Stress in the metal line is a function of ILD (inter-layer dielectric) properties, ILD stack and metal line width. The concept of a SM Risk Index is proposed to assess BEoL stress migration reliability from the stress perspective. Comparison of the SM Risk Index for Cu/FTEOS and Cu/low-k shows that the latter is more prone to stress induced voiding. Stress migration tests verify that MTF values decrease with increasing line width. Modeling results are consistent with experimental findings, while providing more insightful understanding of stress-driven mechanisms in stress migration.

Optimizing the electromigration performance of copper interconnects

The effects of changes in linewidth, barrier type and anneal temperature on electromigration (EM) reliability of inlaid Cu interconnect lines were investigated. Methods developed for quantifying changes in grain size and orientation with changes in processing are detailed and applied to understand their impact on electromigration. While interfaces and microstructure both play a role in Cu reliability, interface diffusion is the dominant effect. For a constant interface and linewidth, grain size is shown to affect reliability.

Effects of active atomic sinks and reservoirs on the reliability of Cu/low-K interconnects

Electromigration experiments using Cu∕low-k interconnect tree structures were carried out in order to study the effects of active atomic sinks and reservoirs on interconnect reliability. In all cases, failures occurred after a long period of void growth. Kinetic parameters were extracted from resistance versus time data, giving (Dz*)0,eff=3.9×10−10m2∕s and z*=0.40±0.12. By using these values, the evolution of stress in each of the interconnect tree segments could be calculated and correlated with the rate of void growth and failure times for all test configurations. It is demonstrated that segments that serve as atomic sinks and reservoirs for the failing segments affect the lifetime by modifying the conditions for stress induced migration. Reservoirs can lead to increased lifetimes, while sinks can lead to reduced lifetimes. Quantitative predictions of the times required for failure for Cu∕low-k interconnect trees as a function of the effective bulk elastic modulus of the interconnect system, B, are made...

The effect of current direction on the electromigration in short-lines with reservoirs

We have conducted electromigration tests on Cu/low-k standard short-line structures as well as those with varying numbers of reservoirs. We found that the presence and number of reservoirs as well as current direction relative to the reservoir led to markedly different electromigration performance in terms of lifetime and distribution shape. That is, in the case of a reservoir by the anode (or electron sink) line-end, lifetimes were similar or slightly better than the In the case of a reservoir by the cathode (or electron source) line-end, lifetimes were extremely longer than the long-line case or even immortal. Further, the distribution of the cathode reservoir structure exhibited a roll-over shape, in which the first fails corresponded to small void sizes and the later fails corresponded to larger void sizes. We believe these observations are related to the differences in stress development during electromigration, which will be constrained at the line-end at which the reservoir is present, and has been verified through simulation. Finally, we propose a method for assigning an equivalent length to these complex short-line configurations which indicates a ldquostrengthrdquo of the short-line benefit which would be equivalent to that of a standard short-line.

TDDB Kinetics and their Relationship with the E- and √E-models

Time-dependent dielectric breakdown (TDDB) studies on advanced Cu/low-k interconnects show that activation energy and voltage acceleration are dependent on stress voltage and temperature respectively. These dependencies can be explained by the E- and √E-models and have important implications on the appropriate test regime for accurate lifetime projections.