Dave Grider

A 4H Silicon Carbide Gate Buffer for Integrated Power Systems

A gate buffer fabricated in a 2-μm 4H silicon carbide (SiC) process is presented. The circuit is composed of an input buffer stage with a push-pull output stage, and is fabricated using enhancement mode N-channel FETs in a process optimized for SiC power switching devices. Simulation and measurement results of the fabricated gate buffer are presented and compared for operation at various voltage supply levels, with a capacitive load of 2 nF. Details of the design including layout specifics, simulation results, and directions for future improvement of this buffer are presented. In addition, plans for its incorporation into an isolated high-side/low-side gate-driver architecture, fully integrated with power switching devices in a SiC process, are briefly discussed. This letter represents the first reported MOSFET-based gate buffer fabricated in 4H SiC.

Experimental switching frequency limits of 15 kV SiC N-IGBT module

This paper presents extensive experimental switching characteristics of a state-of-the-art 15 kV SiC N-IGBT (0.32 cm2 active area) up to 10 kV, 10 A and 175°C. The influence of the thermal resistance of the module package, cooling mechanism, and the increased energy loss with temperature are investigated for determining the switching frequency limits of the IGBT. Detailed FEM analysis is conducted for extracting the thermal resistance of each layer in the 15 kV module from the IGBT junction to the base plate, and then down to the ambient. Using this thermal information and the experimental switching data, the inductive switching frequency limits are analytically evaluated for liquid and air cooling cases with 660 W/cm2 and 550 W/cm2 power dissipation densities respectively, considering 150°C as maximum junction temperature. The air cooling power dissipation density of the 15 kV IGBT is experimentally validated using a dc-dc boost converter at 10 kV, 6.4 kW output and 550 W/cm2 under steady state operating conditions. The gate resistances used for the entire experiments are RG(ON) = 20 Ω and RG(OFF) = 10 Ω.

Comparative Evaluation of 15-kV SiC MOSFET and 15-kV SiC IGBT for Medium-Voltage Converter Under the Same dv/dt Conditions

The 15 kV SiC MOSFET and 15 kV SiC IGBT are two state-of-the-art high voltage SiC devices. These high voltage SiC devices enable simple two level converters for medium voltage source converter compared to the complex three level and multilevel topologies with Silicon devices. This paper presents the detailed experimental results for the characterization of 15 kV SiC MOSFET module at 10 kV and 12 kV DC bus for two different configuration of device under test. This paper also presents the switching loss comparison of 15 kV SiC MOSFET with 15 kV SiC IGBT for the same dv/dt. Based on loss data obtained from experiments, this paper finally reports the switching frequency limits of 15 kV SiC MOSFET for 10 kV DC bus, 3-Phase two level converter and Bi-directional DC-DC phase leg converter with 10 kV output voltage and comparative evaluation of 15 kV SiC MOSFET and 15 kV SiC IGBT for the same dv/dt in a unidirectional DC-DC boost hard switching converter for 10 kV output voltage.

20 kV 4H-SiC N-IGBTs

A 1 cm x 1 cm 4H-SiC N-IGBT exhibited a blocking voltage of 20.7 kV with a leakage current of 140 μA, which represents the highest blocking voltage reported from a semiconductor power switching device to this date. The device used a 160 μm thick drift layer and a 1 μm thick Field-Stop buffer layer, and showed a VF of 6.4 V at an IC of 20 A, and a differential Ron,sp of 28 mΩ-cm2. Switching measurements with a supply voltage of 8 kV were performed, and a turn-off time of 1.1 μs and turn-off losses of 10.9 mJ were measured at 25°C, for a 8.4 mm x 8.4 mm device with 140 μm drift layer and 2 μm F-S buffer layer. The turn-off losses were reduced by approximately 50% by using a 5 μm F-S buffer layer. A 55 kW, 1.7 kV to 7 kV boost converter operating at 5 kHz was demonstrated using the 4H-SiC N-IGBT, and an efficiency value of 97.8% was reported.

1200 V 4H-SiC DMOSFET with an Integrated Gate Buffer

For the first time, a 1200 V 4H-SiC power MOSFET with a monolithically integrated gate buffer circuit has been demonstrated successfully. The device used a 6x1015 cm-3 doped, 10 μm thick n-type drift layer to support 1200 V. The gate buffer circuit was built in a p-well, formed by boron ion implantation. The integrated device provided sufficient voltage isolation for the control circuit from the drain of the power MOSFET, and supported internal supply voltages up to 20 V. The operation of the integrated devices was demonstrated. A specific on-resistance (Ron,sp) of 20 mΩ-cm2 was observed. The high Ron,sp was due to the limitations in NMOS pull-up circuit topology and the body effect in the 4H-SiC NMOSFET. Development of PMOS pull-up devices is recommended for future integration efforts.

Static and Dynamic Characterization of a 3.3 Kv, 45 A 4H-Sic MOSFET

Wide bandgap materials such as Silicon Carbide (SiC) has enabled the use of medium voltage unipolar devices like Metal-Oxide Field Effect Transistors (MOSFETs) and Junction Field Effect Transistors (JFETs), which can switch at much higher frequencies as compared to their silicon counterparts. It is therefore imperative to evaluate the performance of these medium voltage devices. In this paper, the static characterization and the switching performance of the new single die 3.3 kV, 45 A 4H-SiC MOSFET developed by Cree Inc are presented. The switching performance is measured through the conventional Double Pulse Test. Testing is done at a dc-link voltage of 1.5 kV for different values of current, and gate resistances.

Reliability of SiC Power Devices against Cosmic Ray Neutron Single-Event Burnout

High-energy neutrons produced by cosmic ray interactions with our atmosphere are known to cause single-event burnout (SEB) failure in power devices operating at high fields. We have performed accelerated high-energy neutron SEB testing of SiC and Si power devices at the Los Alamos Neutron Science Center (LANCSE). Comparing Wolfspeed SiC MOSFETs having different voltage (900V – 3300V) and current (3.5A – 72A) ratings, we find a universal behavior when scaling failure rates by active area, and scaling drain bias by avalanche voltage. Moreover, diodes and MOSFETs behave similarly, revealing that the SiC drift dominates the failure characteristics for both device types. This universal scaling holds for SiC MOSFETs from other manufacturers as well. The SEB characteristics of Si power IGBT and MOSFET devices show that near their rated voltages failure rates of Si devices can be 10X higher than that of comparable SiC MOSFET devices. Thus, Si devices are more susceptible to SEB failure from voltage overshoot conditions.

Blocking Performance Improvements for 4H-SiC P-GTO Thyristors with Carrier Lifetime Enhancement Processes

An investigation into the increased leakage currents and reduced blocking voltages associated with 1450°C lifetime enhancement oxidation for the 4H-SiC p-GTOs is presented. Roughening of the 4H-SiC surface due to localized crystallization of SiO2, or crystobalite formation, during the high temperature oxidation was identified as one of the main causes of this issue. A factor of 30 difference in permeability to O2 between amorphous SiO2 and crystobalite caused uneven oxidation, which resulted in significant roughness. This roughness, placed at the metallurgical junction between the gate and the drift layer, where the E-field is greatest, is believed to be responsible for the premature breakdown characteristics. A 2-step lifetime enhancement process, which moves this roughness to the lower E-field region of the device was introduced to alleviate this issue. A 15 kV 4H-SiC p-GTO with the 2-step lifetime enhancement process demonstrated a significant reduction in VF over the 1300°C oxidized devices, without any impact on blocking characteristics.

An Analysis of Forward Conduction Characteristics of Ultra High Voltage 4H-SiC N-IGBTs

Ultra High Voltage (UHV) 4H-SiC N-IGBTs, with drift layer thicknesses ranging from 140 μm to 240 μm, were fabricated and characterized. A blocking voltage of 25 kV, and a forward voltage drop (VF) of 12.8 V were measured from a 9 mm x 9 mm device with a 240 μm drift layer. A positive temperature coefficient of VF was observed, which is desirable for paralleling, but unusual for a bipolar device. The cause of this behavior was investigated using a test structure that allowed separate observations of electron and hole currents in the 4H-SiC IGBT structure. It was revealed that the hole current increases with temperature, due to increases in charge injection and carrier lifetimes at elevated temperatures, while the electron current decreases with temperature due to a unipolar resistance component in its path, most likely due to JFET resistance, formed by depletion regions extending into the lightly doped drift region. The concept of Carrier Storage Layer (CSL) was implemented in UHV 4H-SiC N-IGBTs to suppress this effect, resulting in a negative temperature coefficient of VF. A 15 kV 4H-SiC N-IGBT with a 1x1016cm-3 doped CSL showed a VF reduction of 3 V at a collector current of 20 A, at a junction temperature of 150°C, compared to a 15 kV SiC N-IGBT without a CSL at the same collector current value.