David E. Fulkerson

Comments on "Monte Carlo simulation of transport in technologically significant semiconductors of the diamond and zinc-blende structures. II. Submicrometer MOSFETs" [with reply]

For pt.I see ibid., vol.38, no.3, p.634-49, March 1991. MOSFETs with channel lengths smaller than 0.25 mu m with substrates of four different semiconductors and one alloy of the diamond and zinc-blende structures (n-channel Ge, Si, GaAs, InP, In/sub 0.53/Ga/sub 0.47/As, and p-channel Si) were simulated at 77 and 300 K with a self-consistent two-dimensional Monte Carlo program. With the exception of the In-based materials, the speed of the devices appears to be largely independent of the semiconductor. This universal behavior results from the similarity among the medium-energy-scale features of the band structures of the cubic semiconductors. Low-energy concepts, such as mobility and effective mass, fail to describe charge transport as carriers populate a larger fraction of the Brillouin zone in these small devices driven at reasonably high biases. The assumptions made, the approximations used, and, in particular, the meaning of the words speed and reasonably mentioned above are discussed. >

A two-dimensional model for the calculation of common-emitter current gains of lateral p-n-p transistors

Abstract Common-emitter current gains of lateral p - n - p s with and without n + ‘buried layers’ are calculated by solving the two-dimensional diffusion equation (including recombination) in the base region. The proposed computer algorithm can be used for arbitrary emitter and collector junction profiles. The resulting current gains are compared with the predictions of a one-dimensional model and with current gains of experimental lateral p - n - p s.

Modeling Ion-Induced Pulses in Radiation-Hard SOI Integrated Circuits

A common technique for hardening a circuit cell against single-event effects (SEE) is to use an RC delay or other time delay technique to slow down the response of a storage or memory cell. In order for this to work, we must have a good model for the duration of the output voltage pulse due to the ion strike on a given cell. Two-dimensional simulations determine the output voltage pulse shape due to an ion strike on a circuit cell within an integrated circuit. For SOI, the worst-case pulse occurs when the ion strike is near the center of the NMOS body (under the gate). It is very desirable to have a simple SPICE model for the SEE behavior because of the large number of circuit cells that need to be characterized. Two-dimensional (2D) simulations are translated into a ID format, from which closed-form physics-based equations are derived, which are then used in SPICE simulations. Test chips from a 0.15 mum SOI process are used to experimentally determine the LET threshold of six different circuits. The SPICE predictions of LET threshold are in good agreement with the experimental results. Because the SEE pulse widths in SOI circuits are much shorter than those in comparable bulk CMOS circuits, time-delay radiation hardening of SOI can be achieved with much less compromise of the speed of storage or memory cells.

Complementary heterostructure FET technology for low power, high speed digital applications

Abstract A quantitative comparison is given between complementary heterostructure FET (CHFET) and silicon-on-insulator (SOI) complementary logic gates. Using the same power supply (1.3 V), the same gate length (0.7 μm), and the same gate capacitance for the transistors, it is shown that CHFET logic circuits are 2–3 times faster than SOI at the same power, even when driving long on-chip lines. The CHFET logic circuits are 4–9 times lower in power than SOI at the same frequency. The performance advantage of CHFET is due to the high electron velocity in the n-channel transistors. Experimental results of actual CHFET standard cells verify the claims. This paper also shows good agreement between actual CHFET logic performance and the predictions of a SPICE model.

A silicon integrated circuit force sensor

A piezoresistive bridge and integrated circuit amplifier can be made in the same silicon cantilever. The purpose of the amplifier is to linearize as well as amplify the output.

Feedback FET logic: a robust, high-speed low-power GaAs logic family

Feedback FET logic (FFL) with a special output stage that enables it to drive high on-chip capacitances with low power is discussed. FFL is robust in the face of process and temperature variations. The basic FFL gate is a NOR, but complex gates such as AND-OR-NOT are also practical. FFL is two to four times faster than comparable GaAs direct-coupled FET logic and Si CMOS and Si BiCMOS when driving on-chip capacitances that are typical of large ICs. FFL power at 200 MHz is also lower than CMOS and BiCMOS power by a factor of 2 to 4. >

A Physics-Based Engineering Methodology for Calculating Soft Error Rates of Bulk CMOS and SiGe Heterojunction Bipolar Transistor Integrated Circuits

This paper describes a new methodology for characterizing the electrical behavior and soft error rate (SER) of CMOS and SiGe HBT integrated circuits that are struck by ions. A typical engineering design problem is to calculate the SER of a critical path that commonly includes several circuits such as an input buffer, several logic gates, logic storage, clock tree circuitry, and an output buffer. Using multiple 3D TCAD simulations to solve this problem is too costly and time-consuming for general engineering use. The new and simple methodology handles the problem with ease by simple SPICE simulations. The methodology accurately predicts the measured threshold linear energy transfer (LET) of a bulk CMOS SRAM. It solves for circuit currents and voltage spikes that are close to those predicted by expensive 3D TCAD simulations. It accurately predicts the measured event cross-section vs. LET curve of an experimental SiGe HBT flip-flop. The experimental cross section vs. frequency behavior and other subtle effects are also accurately predicted.

An Engineering Model for Single-Event Effects and Soft Error Rates in Bulk CMOS

This paper describes a simple methodology for simulating single-event effects, including soft error rates, of bulk complementary metal-oxide semiconductor integrated circuits. The induced currents due to ion strikes are derived from the basic carrier transport equations and then used in simple SPICE simulations. The 3-D equations were reduced to a 1-D problem. This method is much less expensive than 3-D TCAD for predicting single-event effects, especially when several types of circuits or several critical circuit paths must be investigated. The upset conditions for two SRAMs are simulated, and the results compare well with experiments. A simple method for predicting the soft error rate is also described, including a method for calculating the dimensions of the sensitive volumes for a given circuit.

A simple physical model including velocity overshoot for n-channel heterostructure FETs

A one-dimensional DC model is constructed for n-channel heterostructure FETs. The model includes the velocity versus field relationships, carrier diffusion, and velocity overshoot. The model and experimental data imply that the drain current increases by about 27% by velocity overshoot when the gate length is 1 mu m. >

The characterization of the static behavior of p-n junction devices

This paper examines the static behavior of certain p-n junction devices that are governed by Van Roosbroecks differential equations. It is found that this set of first-order differential equations accurately predicts semiconductor static behavior in both the bulk and the transition regions. The purpose of this model is to find the hole and electron concentrations, hole and electron currents, and electric field as functions of position and external excitation. For part of the paper, use is made of the quasi-neutrality approximation in the bulk regions and the quasi-equilibrium Boltzmann relations (QEBR) which relate the hole and electron concentrations at transition region edges to the applied voltage across the transition region. The unijunction transistor with intrinsic base, p-i and p-in diodes, and a new current gain device are examined using these concepts, and the results are compared with experiment. By applying boundary conditions only at the ohmic contacts, a p-i diode problem is solved on a computer. One especially important point in this problem is that quasi-neutrality of the base and the QEBR are not imposed upon the problem. However, the final results indicate that these concepts are good approximations, except for extremely short devices.