Steven M. Baier

A new and simple model for GaAs heterojunction FET gate characteristics

The gate current-voltage characteristics for modulation-doped field-effect transistors (MODFETs) and heterostructure insulated-gate field-effect transistors (HIGFETs) are described using a simple model. This model, which is physically realistic, consists of two Schottky diodes in series: one is a metal-semiconductor (AlGaAs) Schottky diode and the other is an equivalent Schottky diode due to the heterojunction between the AlGaAs and GaAs. A novel technique is developed to characterize the parameters used for this model. The model is used to estimate the effective electron temperature in the channel close to the drain for MODFETs. The estimated electron temperature with 1 V drain-to-source voltage is as high as 80 degrees C at room temperature. Very good agreement between the calculated and measured results is obtained. This model and characterization technique are also suitable for other heterojunction FETs such as quantum-well MODFETs, etc. >

FET Characterization using gated-TLM structure

A new FET characterization structure consisting of parallel ohmic contacts with gates of varying lengths in between is described. The FET source resistance is accurately measured without parameter fitting or iteration. The low-field electron mobility beneath the gate is determined as an effective uniform value and as a function of distance into the channel without iteration. The use of this structure is demonstrated on self-aligned ion-implanted GaAs MESFETs.

Complementary heterostructure FET technology for low power, high speed digital applications

Abstract A quantitative comparison is given between complementary heterostructure FET (CHFET) and silicon-on-insulator (SOI) complementary logic gates. Using the same power supply (1.3 V), the same gate length (0.7 μm), and the same gate capacitance for the transistors, it is shown that CHFET logic circuits are 2–3 times faster than SOI at the same power, even when driving long on-chip lines. The CHFET logic circuits are 4–9 times lower in power than SOI at the same frequency. The performance advantage of CHFET is due to the high electron velocity in the n-channel transistors. Experimental results of actual CHFET standard cells verify the claims. This paper also shows good agreement between actual CHFET logic performance and the predictions of a SPICE model.

High temperature performance and operation of HFETs

The high temperature performance of Al/sub 0.75/Ga/sub 0.25/As/In/sub 0.25/Ga/sub 0.75/As/GaAs Complementary Heterojunction FETs (CHFETs) is reported between 25 and 500/spl deg/C. Both experimental and modeled devices have shown acceptable digital characteristics to 400/spl deg/C. Digital logic circuits have also been shown to operate at temperatures of over 400/spl deg/C. This strongly suggests that GaAs based devices are capable of satisfying high temperature electronics requirements in the 125-400/spl deg/C range. Two dimensional physically based modeling has been used to understand the high temperature operation of the HFETs. This work has shown that the devices suffer from gate limited drain leakage currents at elevated ambient temperatures. This off-state leakage current is higher than anticipated. Simulation has shown that, although forward gate leakage currents are reduced with the heterostructure device design, the reverse current is not.

Complementary GaAs MESFET logic gates

Operation of the first complementary GaAs MESFET (CMES) logic gates is reported. Direct-coupled inverters utilizing p- and n-channel ion-implanted MESFETs demonstrate good transfer characteristics with less than 5-µW power dissipation per gate. Propagation delays as small as 54 ps are attained in 13-stage ring oscillators at room temperature with speed-power products as small as 6 fJ.

Deep cryogenic noise and electrical characterization of the complementary heterojunction field-effect transistor (CHFET)

This paper discusses a characterization at 4 K of the complementary heterojunction field-effect transistor (CHFET), to examine its suitability for deep cryogenic ( >

The mechanism of subthreshold leakage current in self-aligned gate GaAs MESFET's

The origin of the subthreshold leakage current in self-aligned gate GaAs MESFETs is investigated using temperature characterization, The leakage current is found to be comprised of two components, each dominant in a different temperature range. At temperatures below 0°C, space-charge-limited injection through the surface of the depleted channel dominates. At room temperature and above, the leakage current measured is the ohmic leakage through the bulk substrate. The space-charge-limited injection current is also found to be sensitive to the GaAs substrate quality.

A complementary III–V heterostructure field effect transistor technology for high temperature integrated circuits

Abstract A complementary III–V heterostructure field effect transistor (CHFET) has been developed which employs a high aluminium mole fraction aluminium gallium arsenide (Al 0.75 GaAs) interfacial layer between the gate metallization and the indium gallium arsenide In 0.25 GaAs channel. This produces a quasi-insulating gate structure which reduces the gate leakage current. Experimental and simulation data have been used to show the potential of the CHFET up to temperatures of 500 °C. Computer modelling has also been used to study the role of the heterostructure component parts, which has revealed the relative importance of each material in the successful operation of high temperature electronic devices and facilitated the prediction of further device improvements.

Noise and Electrical Characteristics below 10 K of small CHFET Circuits and Discrete Devices

This paper discusses the latest results of a continuing study of the properties of the complementary heterojunction field-effect transistor (CHFET) at 4 K. The electrical characteristics, including the gate leakage current and the subthreshold transconductance, and the input-referred noise voltage for a new lot of discrete CHFETs is presented and discussed. It is shown that the inclusion of a sidewall spacer on the gate substantially reduced the gate leakage current, as compared to a previous lot without the sidewall spacer. The input-referred noise is approximately the same order of magnitude as previous devices, on the order of 1 (mu) V/(root)Hz at 10 Hz for subthreshold operation. The noise is relatively unaffected by changes in the bias current and drain voltage, but decreases with increasing device size, and is increased by the inclusion of dopants in the channel region. Several simple multiplexer circuits using CHFETs are presented, and the open-loop transfer curve of a multiplexed single gain stage operational amplifier at 4 K is shown.

An analysis of the temperature dependence of the gate current in complementary heterojunction field-effect transistors

The temperature dependence of the gate current versus the gate voltage in complementary heterojunction field-effect transistors (CHFETs) is examined. An analysis indicates that the gate conduction is due to a combination of thermionic emission, thermionic-field emission, and conduction through a temperature-activated resistance. The thermionic-field emission is consistent with tunneling through the AlGaAs insulator. The activation energy of the resistance is consistent with the ionization energy associated with the DX center in the AlGaAs. Methods to reduce the gate current are discussed.<<ETX>>