David Fritsche

Analysis and Design of a Stacked Power Amplifier With Very High Bandwidth

In order to simplify and optimize the design process of stacked amplifiers, this paper presents a novel analytical method to dimension the input network for ideal output behavior. To verify this new structural design process, a fully integrated stacked power amplifier (PA) in 0.25-μm SiGe BiCMOS technology is proposed. The stacked architecture enables broadband matching networks, therefore the designed PA reaches a very high bandwidth of 800 MHz around 2 GHz. At 2 GHz, the small-signal gain is 23.8 dB. The output power in the 1-dB compression point and the saturated output power are 26.2 and 27.3 dBm, leading to a power-added efficiency (PAE) of 34% and 40%, respectively. Using a long-term evolution (LTE) modulated input signal without any predistortion, the amplifier reaches an average output power of 21 dBm and a PAE of 12%, fulfilling the LTE specifications in terms of adjacent channel leakage ratio and error vector magnitude.

A Broadband 200 GHz Amplifier with 17 dB Gain and 18 mW DC-Power Consumption in 0.13

This letter presents a 200 GHz amplifier for low-power high data-rate wireless communications. With large bandwidth and energy efficiency as concurrent goals, cascode stages for high power gain and dual-band matching networks to maximize the bandwidth have been employed. The resulting amplifier has been implemented in a 450 GHz SiGe BiCMOS technology, requiring a circuit area of only 800 μm × 300 μm. The characterized circuit exhibits 16.9 dB of maximum power gain, 44 GHz of bandwidth and -3.5 dBm of output power at 1 dB compression, while requiring only 18 mW of DC-power.

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This paper presents a travelling-wave amplifier (TWA) for wideband applications implemented in a 0.13 µm SiGe BiCMOS technology (ft = 300 GHz, fmax = 500 GHz). The gain cell employed in the TWA is designed to compensate the transmission-line- losses at high frequencies in order to extend the bandwidth as well as the gain bandwidth product (GBP). A gain of 10 dB and a 3-dB bandwidth of 170 GHz are measured for the fabricated TWA. The chip has a chip area of 0.38 mm² and a power consumption of 108 mW. Compared against the state of the art, the presented design achieves the highest reported GBP per area and power consumption.

m SiGe BiCMOS

This letter presents an active 200 GHz fundamental down-conversion mixer based on the Micromixer topology for low-power high data-rate wireless communications. The mixer-core operation requires a -5 dBm LO-signal, which is generated on-chip from an external single-ended source of only -20 dBm by means of a power-efficient LO-driver and a passive balun. Mixer, LO-driver and balun have been implemented together in a 450 GHz SiGe BiCMOS technology occupying a circuit core area of 0.21 mm2. For a 200 GHz LO-signal, the characterized circuit exhibits a maximum conversion gain of 5.5 dB over a 3 dB RF-bandwidth of 30 GHz, requiring only 17.4 and 22.5 mW of DC-power in the mixer core and in the LO-driver, respectively.

170 GHz SiGe-BiCMOS Loss-Compensated Distributed Amplifier

This paper presents the design and characterization of a 24-GS/s 3-bit single-core flash analog-to-digital converter (ADC) in 28-nm low-power digital CMOS. It shows the design study of the track-and-hold circuit and subsequent buffer stage and provides equations for bandwidth calculations without extensive circuit simulations. These results are used to target leading-edge speed performance for a single ADC core. The ADC is capable of achieving its full sampling rate without time interleaving, which makes it the fastest single-core ADC in CMOS reported to date to the best of our knowledge. With a power consumption of 0.4 W and an effective number of bits of 2.2 at 24 GS/s, the ADC achieves a figure of merit of 3.6 pJ per conversion step while occupying an active area of 0.12 mm2. Due to its high sampling frequency this ADC can enable ultra-high-speed ADC systems when combined with moderate time interleaving.

A Low-Power Broadband 200 GHz Down-Conversion Mixer with Integrated LO-Driver in 0.13

This paper presents the design and characterization of a 24 GS/s, 3 bit flash ADC in 28nm low-power (LP) digital CMOS. The circuit was designed with the goal of achieving speed performance above state of the art for a single ADC core. The ADC is capable of delivering its full sampling rate without time interleaving, which makes it the fastest single core ADC in CMOS reported to date to the best of our knowledge. With a power consumption of 406mW and an effective number of bits (ENOB) of 2.2 at 24 GS/s, the ADC achieves a figure of merit (FOM) of 3.6 pJ per conversion step, which is the lowest reported value for single-core ADCs operating above 15 GHz. The very high sampling rate of the presented ADC enables ultra-high-speed ADC systems through moderate time interleaving.

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This paper presents the design and characterization of a 10 GS/s track and hold amplifier (THA). The circuit was fabricated in a 28 nm CMOS technology. It is based on a switched capacitor approach. At a sampling rate of 10 GS/s, the total harmonic distortion is -38dBc with a 3.75 GHz input signal. The chip includes an active balun and buffer stages for the clock signal and consumes 50 mW, which is significantly lower than the state-of-the-art at similar performance. It can work with maximum peak-to-peak differential input voltages of up to 800 mV, which is the highest reported for high-speed CMOS implementations and comparable with the performance of state-of-the-art bipolar implementations.

m SiGe BiCMOS

Enabling the vast computational and throughput requirements of future high performance computer systems and data centers requires innovative approaches. In this paper, we will focus on the communication between computer boards. One alternative to the bottleneck presented by copper wire based cable-bound communication is the deployment of wireless links between nodes consisting of processors and memory on different boards in a system. In this paper, we present an interdisciplinary approach that targets an integrated wireless transceiver for short-range ultra-high speed computer board-to-board communication. Based on our achieved results and current developments, we will also estimate energy consumption of such a transceiver.

Design and Characterization of a 3-bit 24-GS/s Flash ADC in 28-nm Low-Power Digital CMOS

This paper presents a 190-GHz direct conversion transceiver (TRX) chipset with on-chip antennas implemented in a 130-nm SiGe BiCMOS technology for short-distance high-data-rate wireless links. The transmitter (TX) consists of an active fundamental upconversion mixer, a local oscillator (LO) driver, and a passive balun for differential to single-ended conversion of the RF signal. The receiver (RX) is composed of a low-noise amplifier, an active fundamental mixer, an LO driver, a variable-gain baseband (BB) amplifier, and a totem-pole output stage. The wireless communication between TX and RX is enabled by on-chip monopole antennas, which are fabricated using standard wire-bonding tools. Measurements of the TRX chipset equipped with these antennas show a 6-dB BB link bandwidth of 20 GHz, corresponding to 40 GHz of the RF link bandwidth. In a data transmission test setup based on a BPSK modulation, data rates of up to 40 Gbit/s over 20 mm and up to 50 Gbit/s over 6 mm are demonstrated. Consuming only 122 mW in the RX and 32 mW in the TX, this leads to a very low required energy per transferred bit of 3.9 and 3.1 pJ for the 40- and 50-Gbit/s link, respectively.

A 24 GS/s single-core flash ADC with 3 bit resolution in 28 nm low-power digital CMOS

This paper presents a 190-GHz direct-conversion receiver capable of supporting higher-order modulation schemes and implemented in a SiGe BiCMOS technology. The circuit consists of a low-noise amplifier, an active fundamental mixer, a LO driver, a variable-gain baseband amplifier and a totem-pole output stage. To exploit the advantages of sub-THz frequencies in terms of available bandwidth at a low DC power consumption, all circuit blocks are concurrently optimized for large bandwidth and high power-efficiency. While consuming only 122 mW of DC power, the fabricated circuit exhibits a record 3-dB RF bandwidth of 35 GHz, a maximum conversion gain of 47 dB, a maximum baseband voltage swing of more than 800 mVpp and a minimum double-sideband noise figure of 10.7 dB.