Gregor Tretter

A Low-Power Broadband 200 GHz Down-Conversion Mixer with Integrated LO-Driver in 0.13

This letter presents an active 200 GHz fundamental down-conversion mixer based on the Micromixer topology for low-power high data-rate wireless communications. The mixer-core operation requires a -5 dBm LO-signal, which is generated on-chip from an external single-ended source of only -20 dBm by means of a power-efficient LO-driver and a passive balun. Mixer, LO-driver and balun have been implemented together in a 450 GHz SiGe BiCMOS technology occupying a circuit core area of 0.21 mm2. For a 200 GHz LO-signal, the characterized circuit exhibits a maximum conversion gain of 5.5 dB over a 3 dB RF-bandwidth of 30 GHz, requiring only 17.4 and 22.5 mW of DC-power in the mixer core and in the LO-driver, respectively.

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This paper presents the design and characterization of a 24-GS/s 3-bit single-core flash analog-to-digital converter (ADC) in 28-nm low-power digital CMOS. It shows the design study of the track-and-hold circuit and subsequent buffer stage and provides equations for bandwidth calculations without extensive circuit simulations. These results are used to target leading-edge speed performance for a single ADC core. The ADC is capable of achieving its full sampling rate without time interleaving, which makes it the fastest single-core ADC in CMOS reported to date to the best of our knowledge. With a power consumption of 0.4 W and an effective number of bits of 2.2 at 24 GS/s, the ADC achieves a figure of merit of 3.6 pJ per conversion step while occupying an active area of 0.12 mm2. Due to its high sampling frequency this ADC can enable ultra-high-speed ADC systems when combined with moderate time interleaving.

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This paper presents the design and characterization of a 24 GS/s, 3 bit flash ADC in 28nm low-power (LP) digital CMOS. The circuit was designed with the goal of achieving speed performance above state of the art for a single ADC core. The ADC is capable of delivering its full sampling rate without time interleaving, which makes it the fastest single core ADC in CMOS reported to date to the best of our knowledge. With a power consumption of 406mW and an effective number of bits (ENOB) of 2.2 at 24 GS/s, the ADC achieves a figure of merit (FOM) of 3.6 pJ per conversion step, which is the lowest reported value for single-core ADCs operating above 15 GHz. The very high sampling rate of the presented ADC enables ultra-high-speed ADC systems through moderate time interleaving.

Design and Characterization of a 3-bit 24-GS/s Flash ADC in 28-nm Low-Power Digital CMOS

This paper presents the design and characterization of a 10 GS/s track and hold amplifier (THA). The circuit was fabricated in a 28 nm CMOS technology. It is based on a switched capacitor approach. At a sampling rate of 10 GS/s, the total harmonic distortion is -38dBc with a 3.75 GHz input signal. The chip includes an active balun and buffer stages for the clock signal and consumes 50 mW, which is significantly lower than the state-of-the-art at similar performance. It can work with maximum peak-to-peak differential input voltages of up to 800 mV, which is the highest reported for high-speed CMOS implementations and comparable with the performance of state-of-the-art bipolar implementations.

A 24 GS/s single-core flash ADC with 3 bit resolution in 28 nm low-power digital CMOS

Enabling the vast computational and throughput requirements of future high performance computer systems and data centers requires innovative approaches. In this paper, we will focus on the communication between computer boards. One alternative to the bottleneck presented by copper wire based cable-bound communication is the deployment of wireless links between nodes consisting of processors and memory on different boards in a system. In this paper, we present an interdisciplinary approach that targets an integrated wireless transceiver for short-range ultra-high speed computer board-to-board communication. Based on our achieved results and current developments, we will also estimate energy consumption of such a transceiver.

10-GS/s track and hold circuit in 28 nm CMOS

This paper presents a 190-GHz direct-conversion receiver capable of supporting higher-order modulation schemes and implemented in a SiGe BiCMOS technology. The circuit consists of a low-noise amplifier, an active fundamental mixer, a LO driver, a variable-gain baseband amplifier and a totem-pole output stage. To exploit the advantages of sub-THz frequencies in terms of available bandwidth at a low DC power consumption, all circuit blocks are concurrently optimized for large bandwidth and high power-efficiency. While consuming only 122 mW of DC power, the fabricated circuit exhibits a record 3-dB RF bandwidth of 35 GHz, a maximum conversion gain of 47 dB, a maximum baseband voltage swing of more than 800 mVpp and a minimum double-sideband noise figure of 10.7 dB.

Energy-Efficient Transceivers for Ultra-Highspeed Computer Board-to-Board Communication

This paper presents a 190-GHz direct-conversion receiver capable of supporting higher order modulation schemes and implemented in a 130-nm SiGe BiCMOS technology. The circuit consists of a low-noise amplifier, an active fundamental mixer, a local-oscillator driver, a variable-gain baseband (BB) amplifier, and a totem-pole output stage. To exploit the advantages of sub-THz frequencies in terms of available bandwidth (BW) at a low dc power consumption, all circuit blocks are concurrently optimized for large BW and high power efficiency. A high and tunable conversion gain as well as a large maximum BB voltage swing is targeted to allow direct operation with state-of-the-art analog-to-digital converters. While consuming only 122 mW of dc power, the fabricated circuit exhibits a record 3-dB RF BW of 35 GHz, a maximum conversion gain of 47 dB with a tuning range of 20 dB, a maximum BB voltage swing of more than 800

A low-power SiGe BiCMOS 190 GHz receiver with 47 dB conversion gain and 11 dB noise figure for ultra-large-bandwidth applications

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A Low-Power SiGe BiCMOS 190-GHz Receiver With 47-dB Conversion Gain and 11-dB Noise Figure for Ultralarge-Bandwidth Applications

, and a minimum double-sideband noise figure of 10.7 dB.

A 55-GHz-Bandwidth Track-and-Hold Amplifier in 28-nm Low-Power CMOS

This brief presents a 25-GS/s track-and-hold amplifier (THA) implemented in a 28-nm low-power digital CMOS process. Given the intrinsic low-pass behavior of the THA core, a frequency compensation technique is employed to improve the bandwidth by increasing the input amplitude for higher frequencies. This enhances the small-signal bandwidth by almost 30% to 70 GHz. Large-signal measurements show a 3-dB corner frequency of 55 GHz, which enables a performance sufficient for time-interleaved analog-to-digital converter systems operating above 100 GS/s. At a peak-to-peak input amplitude of 400 mV, the total harmonic distortion is -32 dB for a 50-GHz input signal at a dc power consumption of 73 mW.