David G. Figueroa

A new technique for high frequency characterization of capacitors

To improve the accuracy for high frequency characterization of capacitors with very low inductance values, a technique is developed. The first part of the technique requires a standard calibration for a network analyzer. Then s-parameter measurements for test fixtures and adapters are measured. A high frequency circuit model for every connector or test fixture from the calibrated port to the device under test (DUT) is then de-embedded one at a time, using the measured data as a reference and each time adding in the previously de-embedded circuit model. The difference between the measured data and the simulated data is forced to be less than 1%. This stringent requirement is necessary for obtaining the high accuracy equivalent series inductance (ESL) and resistance (ESR). The requirement also guarantees the accuracy of high frequency parasitic capacitance and resistance of a capacitor. After the high frequency circuit models for all test fixtures and adapters are found, s-parameter measurements for a capacitor mounted on a test fixture with an adapter are measured. When the circuit models for the test fixture and adapter are put together and the whole system is matched to the measured s-parameter data for the whole system, the circuit model of a capacitor has been found. In this paper, two new capacitor models and several discontinuity models are also reported. The new capacitor models are valid for the entire frequency range. The discontinuity models are fully consistent with the real physical structure of test fixtures. Different capacitors from various suppliers are characterized and the high frequency circuit models are also provided.

Enhancing power distribution system through 3D integrated models, optimized designs, and switching VRM model

After conducting 3D integrated modeling of an Intel microprocessor, a distributed load current model represented the non-uniform power distribution on the chip is hooked up the on-chip interconnect. The on-chip interconnect is then tied to the integrated model. A multiple-phase, full synchronous switched dc/dc converter model is connected to the other end of the integrated model. Performance evaluation of the complete power delivery system based on a single and multiphase dc/dc converter is made. Advantages and disadvantages of each design are noted. Differences in the output characteristics with a simple source replacement of the dc source and with an actual voltage regulator module are highlighted.

Design and performance evaluation of chip capacitors on microprocessor packaging

This paper describes the different chip capacitor placement design on Intels latest Celeron CPU package. The evaluation of its effectiveness in the power delivery network and final impact on CPU performance are also discussed.

Validation of integrated capacitor-via-planes model

As clock speeds increase into the GHz regime and rise times decrease into the picosecond regime, the interaction between capacitors and the power/ground planes of the package, interposer, or board on which they are mounted becomes vitally important to the performance of a power delivery system. To include the interaction, this paper provides an integrated model for a discrete capacitor mounted on pads over vias connected to power/ground planes with degassing holes. The mutual inductance between capacitor pads, vias, and power/ground planes are completely modeled. Our modeling results show that the mutual inductance drastically changes the total loop inductance as compared to the self inductance of the capacitor. In some cases, it even reduces the total effective loop inductance. To validate the integrated modeling method, a test package is built. A measurement technique is introduced to evaluate the total loop inductance of the test package with various capacitors. The predicted results matched very well with measured data which give a high confidence on this predicting model and demonstrate the importance of modeling the interaction between capacitors, vias, and planes.

A technique for the characterization of multi-terminal capacitors for high frequency applications

This paper discusses the characterization of multi-terminal capacitors through a range of frequencies that have a known importance to leading microprocessor technologies. This will cover the measurement of the capacitor by itself, and the de-embedding and analysis of the component to ensure the data only contains the part being measured and not the system on which it is measured, as well as the capacitor in a system. In addition, the techniques discussed for the system mounted capacitor will be supported with modeling.